Test
PCA_Final [arc2-1, Part-1]
Preguntas del test (128)
1Storage Systems, “Higher associativity to reduce miss rate”
- AThe simplest way to reduce the miss rate to take advantage of spatial locality and increase the block size
- BThe obvious way to reduce capacity misses is to increase cache capacity
- CObviously, increasing associativity reduces conflict misses
2How many Optimizations’ in Cache memory Performance?
- A6
- B8
- C10
3Storage Systems, “Larger block size to reduce miss rate”
- AThe simplest way to reduce the miss rate to take advantage of spatial locality and increase the block size
- BThe obvious way to reduce capacity misses is to increase cache capacity
- CObviously, increasing associativity reduces conflict misses
4What is the “Read Operands” in simple five-stage pipeline?
- AWait until no data hazards, then reads the operand
- BDecode instructions, check for structural hazards
5Storage Systems, “Bigger caches to reduce miss rate”
- AThe simplest way to reduce the miss rate to take advantage of spatial locality and increase the block size
- BThe obvious way to reduce capacity misses is to increase cache capacity
- CObviously, increasing associativity reduces conflict misses
6Tenth optimization of Cache Memory “Register prefetch”?
- ALoads data only into the cache and not the register
- BWill load the value into register
7At storage systems Gray and Siewiorek classify faults what does mean “Operation faults”?
- ADevices that fail, such as perhaps due to an alpha particle hitting a memory cell
- BFaults in software (usually) and hardware design (occasionally)
- CMistakes by operations and maintenance personnel
8What is a “Kernel” in Cache Memory?
- AExecution or waiting for synchronization variables
- BExecution in user code
- CExecution in the OS that is neither idle nor in synchronization access
9Little’s Law and a series of definitions lead to several useful equations for “Time queue” -
- AAverage time per task in the queue
- BAverage time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
- CAverage time/task in the system, or the response time, which is the sum of Time queue and Time server
10How many steps took Virtual Machine Monitor to improve performance of virtual machines?
- A5
- B3
- C4
11How many issue queue used in Centralized Superscalar 2 and Exceptions
- A4
- B3
- C2
- D1
12Which of the following formula is true about Issue Queue for “Instruction Ready”
- AInstruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no structural hazards
- BInstruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc1)&& no structural hazards
- CInstruction Ready = (!Vsrc0 || !Psrc1)&&(!Vsrc1 || !Psrc0)&& no structural hazards
- DInstruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc0)&& no structural hazards
13What is the “Read Operands” in Pipelining Basics?
- AWait until no control hazards, then reads the operand
- BWait until no structural hazards, then reads the operand
- CWait until no data hazards, then reads the operand
14Perfect caches at The Hardware Model?
- AAll memory accesses take one clock cycle
- BAll conditional branches are predicted exactly
- CAll memory addresses are known exactly
15How many stages used in Superscalar (Pipeline)?
- A4
- B5
- C6
- D7
16How much in percentage single-processor performance improvement has dropped to less than?
- A22%
- B33%
- C11%
17What is “VLIW”?
- AVery Long Instruction Word
- BVery Less Interpreter Word
- CVery Light Internal Word
- DVery Low Invalid Word
18At VLIW by “performance and loop iteration” which time is shorter?
- ASoftware Pipelined
- BLoop Unrolled
19Little’s Law and a series of definitions lead to several useful equations for “Time server” -
- AAverage time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
- BAverage time per task in the queue
- CAverage time/task in the system, or the response time, which is the sum of Time queue and Time server
20What single-processor performance improvement has dropped?
- A2004
- B2002
- C2003
21What does MAF?
- AMiss Address File
- BMap Address File
- CMemory Address File
22How many classes of computers classified?
- A3
- B5
- C7
23Sixth Optimization of Cache Memory “Critical word first”?
- AFetch the words in normal order, but as soon as the requested word of the block arrives send it to the processor and let the processor continue execution
- BRequest the missed word first from memory and send it to the processor as soon as it arrives, let the processor continue execution while filling the rest of the words in the block
24In an important early study of intrusion, Anderson[ANDE80] identified three classes of intruders:
- AControl, exploit, system
- BMasquerader, misfeasor, clandestine user
- CIndividual, legitimate, authorized
- DOutside, inside, offside
25How many elements of the Instruction Set Architecture (ISA):
- A7
- B8
26What is the “Bigger caches to reduce miss rate” at Basics of Memory Hierarchies
- AThe obvious way to reduce capacity misses is to increase cache capacity
- BObviously, increasing associativity reduces conflict misses
27At storage systems Gray and Siewiorek classify faults what does mean “Design faults”?
- ADevices that fail, such as perhaps due to an alpha particle hitting a memory cell
- BFaults in software (usually) and hardware design (occasionally)
- CMistakes by operations and maintenance personnel
28What is the ARF?
- AArchitectural Register File
- BArchitecture Relocation File
- CArchitecture Reload File
- DArchitectural Read File
29What is the Conflict in main categories in Cache Memory?
- Afirst-reference to a block, occur even with infinite cache
- Bmisses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
- Ccache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
30Non-Blocking Cache Timeline for “Miss Under Miss” the sequence is?
- ACPU time->Cache Miss->Miss->Stall on use->Miss Penalty->Miss Penalty->CPU time
- BCPU time-Cache Miss-Miss Penalty-CPU time
- CCPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
31At VLIW “Superscalar Control Logic Scaling” which parameters are used?
- AWidth and Lifetime
- BWidth and Height
- CTime and Cycle
- DLength and Addition
32What is a “Synchronization” in Cache Memory?
- AExecution in the OS that is neither idle nor in synchronization access
- BExecution in user code
- CExecution or waiting for synchronization variables
33 Non-Blocking Cache Timeline for “Blocking Cache” the sequence is?
- ACPU time-Cache Miss-Miss Penalty-CPU time
- BCPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
- CCPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time
34Flash memory is a type of?
- AElectronically Erasable Programmable Read-Only Memory
- BElectronically Extensible Programmable Re-Order Memory
- CElectronically Executable Programmable Reduce Memory
35 Access time at memory latency is -
- AThe time between when a read is requested and when the desired word arrives
- BThe minimum time between unrelated requests to memory
36In Multilevel Caches “Local miss rate” equals =
- Amisses in cache / accesses to cache
- Bmisses in cache / CPU memory accesses
- Cmisses in cache / number of instructions
37What is a RAID 1?
- AAlso called mirroring or shadowing, there are two copies of every piece of data
- BIt has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
- CThis organization was inspired by applying memory-style error correcting codes to disks
38RAW (read after write)?
- AThis hazard corresponds to an output dependence
- BThis hazard is the most common type and corresponds to a true data dependence
- CThis hazard arises n antidependence (or name dependence)
39How many size of Cache L3 is true approximately?
- A3 MB
- B256 MB
- C256 KB
40What is a RAID 3?
- ASince the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed
- BMany applications are dominated by small accesses
- CAlso called mirroring or shadowing, there are two copies of every piece of data
41What is the increasing cache bandwidth?
- ACritical word first and merging write buffer
- BPipelined caches, multibanked caches and non-blocking caches
- CSmall and simple first-level caches and way-prediction
42 What is RAID 2?
- AThis organization was inspired by applying memory-style error correcting codes to disks
- BIt has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
- CAlso called mirroring or shadowing, there are two copies of every piece of data
43In Non-Blocking Caches what does mean “Critical word first”?
- ARequest the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
- BFetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
44Sixth optimization of cache memory “Early restart”?
- AFetch the word in normal order, but as soon as the requested word of the block arrives send it to the processor and let the processor continue execution
- BRequest the missed word first from memory and send it to the processor as soon as it arrives, let the processor continue execution while filling the rest of the words in the block
45How many size of Cache L2 is true approximately?
- A256 KB
- B4 KB
- C32 MB
46Reducing the miss penalty or miss rate via parallelism?
- AHardware prefetching and compiler prefetching
- BCompiler optimization
- CPipelined caches, multibanked caches and non-blocking caches
47What is a RT?
- ARename Table
- BRecall Table
- CRelocate Table
- DRemove Table
48How many functions at integrated instruction fetch units?
- A3
- B4
- C5
49What is the PMD in computer classes?
- APercentage map device
- BPersonal mobile device
- CPowerful markup distance
- DPeak maze development
50The second type of dependence is?
- AData dependence
- BName dependence
- CControl dependence
51How many elements presented at performance trends: bandwidth over latency?
- A4
- B5
- C3
52What is the compulsory in main categories in cache memory?
- ACache is too small to hold all data needed by program, occur even under perfect replacement policy(loop over 5 cache lines)
- BMisses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
- CFirst-reference to a block, occurs even with infinite cache
53How many elements in trends of technology?
- A5
- B4
- C6
54Perfect memory address alias analysis at the Hardware model?
- AAll conditional branches are predicted exactly
- BAll memory accesses take one clock cycle
- CAll memory addresses are known exactly
55Speculating on exceptions “Recovery mechanism” is –
- AExceptions are rare, so simply predicting no exceptions is very accurate
- BOnly write architectural state at commit point, so can throw away partially executed instructions after exception
- CNone of them
- DAn entity capable of accessing objects
56What is the reducing the miss rate?
- AWhat is the reducing the miss rate?
- BPerformance optimization
- CCompiler optimization
- DTime optimization
57DDR is –
- ADouble data rate
- BDensity data rate
- CDynamic data rate
58In Non-blocking caches what does mean “Early restart”?
- AFetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
- BRequest the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
59Which distance of price has clusters/warehouse-scale computers?
- A100-100 000$
- B100 000-200 000 000$
- C5 000 -10 000 000$
60Little’s Law and a series of definitions lead to several useful equations for “Time System”-
- AAverage time/task in the system, or the response time, which is the sum of Time queue and Time server
- BAverage time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
- CAverage time per task in the queue
61What is the MISD one of the categories of computers?
- AMultiple instructions streams, set data stream
- BMultiple instructions streams, single data stream
- CMultiple instruction stream, multiple data streams
62What is a RAID 4?
- AMany applications are dominated by small accesses
- BSince the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed
- CAlso called mirroring or shadowing, there are two copies of every piece of data
63Tenth Optimization of cache memory “Cache prefetch”?
- AWill load the value into a register
- BLoads data only into the cache and not the register
64What is the Request level parallelism?
- AExploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
- BExploits parallelism among largely decoupled tasks specified by the programmer or the operating system
- CExploit data-level parallelism by applying a single instruction to a collection of data in parallel.
65Non-blocking cache timeline for “Hit under miss” the sequence is -?
- ACPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
- BCPU time-Cache Miss-Miss Penalty-CPU time
- CCPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time
66At storage systems Gray and Siewiorek classify faults what does mean “Hardware faults”?
- ADevices that fail, such as perhaps due to an alpha particle hitting a memory cell
- BFaults in software (usually) and hardware design (occasionally)
- CMistakes by operations and maintenance personnel
67WAR(write after read)?
- AThis hazard correspond to an output dependence
- BThis hazard arises from an antidependence (or name dependence)
68Main term of dependability is SLAs?
- AScale level approach
- BService level agreements
- CStandard level achievement
69At VLIW by “performance and loop iteration” which time is longer?
- ALoop unrolled
- BSoftware Pipelined
70What is the temporal locality?
- AExploit by remembering the contents of recently accessed locations
- BExploit by fetching blocks of data around recently accessed locations
71What is an IQ?
- AIssue Queue
- BInternal Queue
- CInterrupt Queue
- DInstruction Queue
72If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time”-?
- AThe time between when the user enters the command and the complete response is displayed
- BThe time for the user to enter the command
- CThe time from the reception of the response until the user begins to enter the next command
73How many size of Cache L1 is true approximately?
- A8 KB
- B256 KB
- C2 MB
74What is a RISC computers?
- AReduced instruction set computer
- BResearch interconnect several computer
- CRational interruptible security computer
75The hardware model represents the assumptions made for an ideal or perfect processor is as how many follow elements?
- A4
- B6
- C5
76What is the “opcode”?
- AOperand code
- BOptional code
- COperation code
77WAW(write after write)?
- AThis hazard arises from an antidependence (or name dependence)
- BThis hazard corresponds to an output dependence
- CThis hazard is the most common type and corresponds to a true data dependence
78What is the Vector Architectures and graphic processor units(GPUs)?
- AExploits parallelism among largely decoupled tasks specified by the programmer or operating system
- BExploit data-level parallelism by applying a single instruction to a collection of data in parallel
- CExploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at medium levels using ideas like speculative execution
79Speculating on exceptions “Check prediction mechanism” is –
- AExceptions detected at end of instruction execution pipeline, special hardware for various exception types
- BExceptions are rare, so simply predicting no exceptions is very accurate
- CThe way in which an object is accessed by a subject
- DNone of them
80At VLIW Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
- ASpeculative operations that don’t cause exceptions
- BHardware to check pointer hazards
81At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion:
- ASpeculative operations that don’t cause exceptions
- BHardware to check pointer hazards
82What is PRF?
- APipeline Register File
- BPhysical Register File
- CPure Register File
- DPending Register File
83Speculation and the Challenge of Energy efficiency consume excess energy in how many ways?
- A3
- B4
- C2
84How many instructions used in Distributed Superscalar 2 and Exceptions?
- A1
- B2
- C3
- D4
85What is about Superscalar means “F-D-X-M-W”?
- AFetch, Decode, Instruct, Map, Write
- BFetch, Decode, Excite, Memory, Write
- CFetch, Decode, Except, Map, Writeback
- DFetch, Decode, Execute, Memory, Writeback
86SDRAM is -
- ASynchronous dynamic random access memory
- BStatic dynamic random access memory
- CSuper dynamic random access memory
87How many restrictions RAW hazards through memory are maintained?
- A3
- B4
- C2
88In Multilevel Caches “Misses per instruction” equals =
- AMisses in cache / number of instructions
- BMisses in cache / accesses to cache
- CMisses in cache / CPU memory accesses
89How many possible Elements of Data Hazards?
- A3
- B6
- C8
90If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Entry time” ?
- AThe time from the reception of the response until the user begins to enter the next command
- BThe time for the user to enter the command
- CThe time between when the user enters the command and the complete response is displayed
91Clock cycle time is -
- AHardware technology and organization
- BOrganization and instruction set architecture
- CInstruction set architecture and compiler technology
92A virus classification by target includes the following categories. What is a File infector?
- AThe key is stored with the virus
- BFar more sophisticated techniques are possible
- CA typical approach is as follows
- DInfects files that the operating system or shell consider to be executable
93What is an ALAT?
- AAddition Long Accessibility Table
- BAllocated Link Address Table
- CAllowing List Address Table
- DAdvanced Load Address Table
94CPI is -
- AHardware technology and organization
- BOrganization and instruction set architecture
- CInstruction set architecture and compiler technology
95What is SB?
- AScaleboard
- BScoreboard
- CScorebased
- DScalebit
96At Critical Word First for miss penalty chose correct sequence of Basic Blocking Cache “Order of fill”:
- A0,1,2,3,4,5,6,7
- B3,4,5,6,7,0,1,2
97At Critical Word First for miss penalty chose correct sequence of Blocking Cache with critical word first “Order of fill”:
- A0,1,2,3,4,5,6,7
- B3,4,5,6,7,0,1,2
98What is a RAID 0?
- AThis organization was inspired by applying memory-style errorcorrecting codes to disks
- Bit has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks”, although the data may be striped across the disks in the array
- CAlso called mirroring or shadowing, there are two copies of every piece of data
99What is a file?
- AIt is the basic element of data
- Bit is a collection of related fields that can be treated as a unit by some application program
- Cit is a collection of related data
- Dit is a collection of similar records
100What is the reducing the miss penalty?
- APipelined caches, multibanked caches, and nonblocking caches
- BCritical word first and merging write buffer
- CSmall and simple first-level caches and way-prediction
101Little’s Law and a series of definitions lead to several useful equations for “length server”-:
- AAverage length of queue
- BAverage number of tasks in service
102At storage systems gray and Siewiorek classify faults what does mean “environmental faults”?
- AFire, flood, earthquake, power failure and sabotage
- BFaults in software (usually) and hardware design (occasionally)
- CDevices that fail, such as perhaps due to an alpha particle hitting a memory cell
103How many types of dependencies do you know?
- A3
- B4
- C5
104How many major flavors in multiple-issue processors?
- A3
- B4
- C5
105Out-of-order control complexity MIPS R10000 which is not in control logic?
- ACLK
- BAddress queue
- CInteger datapath
- DFree list
106At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches
- AAllow one instruction to branch multiple directions
- BSpeculative operations that don’t cause exceptions
107Infinite register renaming at the hardware model?
- AThere are an infinite number of virtual registers available
- BBranch prediction is perfect, all conditional branches are predicted exactly
108What is reducing hit time?
- APipelined caches, multibanked caches, and nonblocking caches
- BCritical word first and merging write buffer
- CSmall and simple first-level caches and way-prediction
109Cycle time at memory latency is -
- AThe time between when a read is requested and when the desired word arrives
- Bthe minimum time between unrelated requests to memory
110Speculating on Exceptions “Prediction mechanism” is
- ANone of them
- Bexceptions are rare, so simply predicting no exceptions is very accurate
- Conly write architecture state at commit point, so can throw away partially executed instructions after exception
- DExceptions detected at end of instruction execution pipeline, special hardware for various exception types
111How many main levels of cache memory?
- A2
- B8
- C3
- D6
112What is the thread level parallelism -
- AExploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads
- BExploits parallelism among largely decoupled tasks specified by the programmer or operating system
- CExploit data-level parallelism by applying a single instruction to a collection of data in parallel
113How many steps in instruction execution?
- A4
- B6
- C3
- D5
114How many issue queue used in Centralized Superscalar 2 and exceptions?
- A2
- B4
- C3
- D1
115What is a FL?
- Afree leg
- Bfree list
- Cfree last
- Dfree launch
116If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time”-?
- AThe time from the reception of the response until the user begins to enter the next command
- Bthe time between when the user enters the command and the complete response is displayed
- Cthe time for the user to enter the command
117What is the “issue” in pipelining basics?
- ADecode instructions, check for data hazard
- BDecode instructions, check for control hazard
- CDecode instructions, check for structural hazard
118Little’s Law and a series of definitions lead to several useful equations for “Length queue”
- AAverage length of queue
- BAverage number of tasks in service
119Perfect jump prediction at The Hardware Model?
- AAll jumps are perfectly predicted
- BAll memory addresses are known exactly
- CBranch prediction is perfect
120What is the term of dependability in SLOs?
- AStandard Level Offset
- BStandard Level Objectives
121What is a FSB?
- AFinished store Buffer
- BFinished stack Buffer
- CFinished star Buffer
- DFinished stall Buffer
122Out-of-order control complexity MIPS R10000 which is in control logic?
- AData tags
- BRegister name
- CInstruction cache
- DData cache
123Instruction count is –
- AOrganization and instruction set architecture
- BHardware technology and organization
- CInstruction set architecture and compiler technology
124What is the Instruction Level Parallelism?
- AExploit data-level parallelism by applying a single instruction to a collection of data in parallel.
- BExploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at a medium levels using ideas like speculative execution.
- CExploits parallelism among largely decoupled tasks specified by the programmer or operating system.
125What is the RLP?
- ARandom Level Parallelism
- BRequest Level Parallelism
- CResearch Level Parallelism
126In multilevel caches “Global miss rate” equals:
- Amisses in cache / CPU memory accesses
- Bmisses in cache / accesses to cache
- Cmisses in cache / number of instructions
127What does mean MSHR?
- AMiss Status Handling Register
- BMemory status handling register
- Cmips status hardware prefetching
- Dmap status handling reload
128What is the spatial locality?
- AExploit by remembering the contents of recently accessed locations
- BExploit by fetching blocks of data around recently accessed locations
Información
- Descripción
- Arc2-1 file's quiz
- Autor
- Good Guy Beket
- Idioma
- English
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