Test
CsaMid1
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Preguntas del test (96)
1A common measure of performance for a processor is the rate at which instructions are executed, called
- ACPI
- BClock Rate
- CMFLOPS
- DMIPS
2A technique used in advanced microprocessors where the microprocessor begins executing a first instruction before the second has been completed is called pipelining
- ATrue
- BFalse
3Choose the features of third generation computer architecture
- AObject-Oriented Programming
- BGraphics
- CTimesharing
- DFloating point arithmetic
- EUse of cache memory
4Choose advanced cache optimizations
- AGiving Reads Priority over Writes
- BLarger Cache Size
- CHardware Prefetching of Instructions and Data
- DMerging Write Buffer
- ECritical Word First and Early Restart
5Choose basic cache optimizations
- ACompiler-Controlled Prefetching
- BNonblocking Caches
- CSmall and Simple First-Level Caches
- DMultilevel Caches
- EAvoiding Address Translation during Cache Indexing
6Choose data dependences
- ARead-After-Read
- BRead-After-Write
- CWrite-After-Write
- DWrite-After-Read
7Choose hazard for the following definition\: an instruction cannot continue because it needs a value that has not yet been generated by an earlier instruction
- AData
- BStructural
- CControl
8Choose hazard for the following definition\: different instructions in different stages (or the same stage) conflicting for the same resource
- AStructural
- BData
- CControl
9Choose hazard for the following definition\: fetch cannot continue because it does not know the outcome of an earlier branch - special case of a data hazard
- AControl
- BStructural
- CData
10Choose the access method
- AParallel Access
- BIndirect Access
- CRandom Access
- DDirect Access
- ESequential Access
11Choose the component of SSD for the following definition\: High speed RAM memory components used for speed matching and to increased data throughput
- AData buffer/cache
- BFlash Memory Components
- CAddressing
- DController
- EError Correction
12Choose the component of SSD for the following definition\: Individual NAND flash chips
- AFlash Memory Components
- BAddressing
- CData buffer/cache
- DController
13Choose the component of SSD for the following definition\: Logic for error detection and correction
- AError Correction
- BAddressing
- CData buffer/cache
- DController
- EFlash memory components
14Choose the component of SSD for the following definition\: Logic that performs the selection function across the flash memory components
- AAddressing
- BFlash Memory Components
- CData buffer/cache
- DController
- EError Correction
15Choose the component of SSD for the following definition\: Logic that performs the selection function across the flash memory components
- AAddressing
- BFlash Memory Components
- CData buffer/cache
- DController
- EError Correction
16Choose the component of SSD for the following definition\: provides SSD device level interfacing and firmware execution
- AController
- BAddressing
- CData buffer/cache
- DError correction
- EFlash memory components
17Choose the components of SSD
- AController
- BAddressing
- CData buffer/cache
- DData size
- EMemory hierarchy
18Choose the definition for capacity misses
- AOccurs if the cache cannot contain all the blocks needed during execution of a program
- BThe very first access to a block cannot be in the cache
- COccurs if the block placement strategy is not fully associative
19Choose the definition for compulsory misses
- AOccurs if the cache cannot contain all the blocks needed during execution of a program
- BOccurs if the block placement strategy is not fully associative
- CThe very first access to a block cannot be in the cache
20Choose the definition for conflict misses
- AOccurs if the block placement strategy is not fully associative
- BOccurs if the cache cannot contain all the blocks needed during execution of a program
- CThe very first access to a block cannot be in the cache
21Choose the element(s) of cache design
- ATag
- BLatency
- CAMAT
- DMapping Function
- EReplacement Algorithm
- FNumber of Caches
22Choose the element(s) of cache design{
- ATag
- BLatency
- CAMAT
- DCache Size
- ELine Size
- FNumber of Caches
23Choose the feature(s) of first generation computer architecture
- AMagnetic core memory
- BSemiconductor memory
- CMachine code
- DVacuum tubes
- EAssembly language
24Choose the feature(s) of fourth generation computer architecture
- AObject-Oriented programming
- BWide spread use of data communications
- CSmallest in size
- DUse of cache memory
- EUse of drum memory or magnetic core memory
25Choose the feature(s) of second generation computer architecture
- AHigh level languages
- BTransistors
- C2 Kb memory, 10 KIPS
- D2 Mb memory, 5 MIPS
- EDifferent types of supported instructions
26Choose the feature(s) of third generation computer architecture
- AObject-Oriented programming
- BFloating point arithmetic
- CGraphics
- DTimesharing
- EUse of cache memory
27Choose the key characteristics of computer memory systems
- ALocation
- BUnit of Transfer
- CAccess Method
- DStalling
- EHazards
28Choose the key characteristics of computer memory systems
- ACapacity
- BPerformance
- COrganization
- DInstruction Fetch
- EInstruction Decode
29Choose the performance factor
- ACache Size
- BLine Size
- CInstruction Count
- DNumber of Processor Cycles
- ENumber of memory references
30Choose the physical characteristic(s) of disk systems
- ADisk system implementstion
- BDisk Size
- CHead Mechanism
- DHead Motion
- EDisk Portability
31Choose the physical characteristic(s) of disk systems
- ADisk system implementstion
- BDisk Size
- CHead Mechanism
- DPlatters
- ESides
32Choose the system attribute(s) by which the performance factors are influenced
- ACache size
- BUnit of Transfer
- CCompiler Technology
- DProcessor Implementation
- ECache and memory hierarchy
33Choose the type(s) of auxiliary memory
- AFlash Memory
- BOptical Disk
- CHard Drive
- DSSD
- ERAM
34Choose the years of the first generation computer architecture
- A1958-1964
- B1964-1974
- C1974-present
- D1945-1964
- E1945-1958
35Choose the years of the second generation computer architecture
- A1964-1974
- B1974-present
- C1958-1964
36Choose two types of models for a computing machine
- AHarvard architecture
- BVon Neumann architecture
- COxford architecture
- DStanford architecture
37CPU Time \= I * CPI / R. Which parameter requires special profiling software
- ACycles Per instruction
- BClock Rate
- CNumbers of instructions
- DExecution time
38Floating point performance is expressed as
- ACPI
- BFLOPS
- CMIPS
- DMFLOPS
39For random-access memory, the time it takes to perform a read or write operation is called
- AClock Rate
- BCPI
- CAccess Time
- DLatency
40Four bits make octal digit
- AVerdadero
- BFalso
41Halting the flow of instructions until the required result is ready to be used is called{
- Awaiting
- Bdelaying
- Chalting
- Dstalling
42How a binary digit is called
- Abyte
- Bdigit
- Ckilobyte
- Dbit
43How a memory unit accessed by contents is called
- AAssociative Memory
- BContent Addressable Memory
- CAuxiliary Memory
- DCache Memory
- EVirtual Memory
44How external nonvolatile memory is called
- ASecondary memory
- BMain memory
- CCache memory
- DVirtual memory
45How many access methods are there
- A3
- B2
- C4
- D6
- E1
46How many elements of cache design are there
- A2
- B5
- C7
- D6
- E4
- F8
47How many generations of computer architecture are there
- A4
- B3
- C2
- D5
48How many number systems are there
- A2
- B3
- C4
49How many performance factors are there
- A5
- B4
- C6
- D3
- E1
50How many physical characteristics of disk systems are there
- A4
- B5
- C6
- D3
51How the stage in which the results of the operation are written to the destination register is called
- AInstruction Fetch
- BWrite Back
- CInstruction Decode
- DExecution
- EMemory read/write
52IBM System/360 Model 91 was introduced in 1966
- AVerdadero
- BFalso
53In 1976 Apple II computer model was released
- AVerdadero
- BFalso
54In LRU replacement algorithm, the block that is in the cache longest is replaced
- AVerdadero
- BFalso
55In virtual memory, memory can be used efficiently because a section of program always loaded
- AVerdadero
- BFalso
56In virtual memory, memory can be used efficiently because a section of program always loaded{
- AVerdadero
- BFalso
57In which cache memory mapping technique any block from main memory can be placed anywhere in the cache
- AAssociative Mapping
- BSet Associative Mapping
- CDirect Mapping
58In which cache memory mapping technique any memory block is mapped to exactly one block in the cache
- ADirect Mapping
- BSet Associative Mapping
- CAssociative Mapping
59In which cache memory mapping technique any memory block mapped to subset of cache locations
- ASet Associative Mapping
- BDirect Mapping
- CAssociative Mapping
60Into how many parts a program (or algorithm) which can be parallelized can be split up
- A3
- B4
- C5
- D2
61Select cache optimizations to reduce miss penalty
- AMultilevel Caches
- BGiving Reads Priority over Writes
- CHigher associativity
- DWay Prediction
62Select cache optimizations to increase the Cache Bandwidth
- ANonblocking Caches
- BMultibanked Caches
- CPipelined Cache Access
- DMultilevel Caches
- ESmall and Simple First-Level Caches
63Octal and hexadecimal numbers are hard on use and conversion
- AVerdadero
- BFalso
64Physical address used by program, and which OS must translate into virtual address
- AVerdadero
- BFalso
65Pipelining can only be implemented on hardware
- AVerdadero
- BFalso
66Process of instruction execution is divided into two or more steps, called
- Apipelining
- Bpipe stages
- Cpipe segments
- Dinstruction execution
- Epipeline hazard
67ROM is the place in a computer where the operating system, application programs, and data in current use are kept
- AVerdadero
- BFalso
68Choose the features of first generation computer architecture
- AVacuum tubes
- BAssembly language
- CMagnetic core memory
- DSemiconductor memory
- EMachine code
69Which type of memory accessed via the input/output channels
- AAuxiliary Memory
- BSecondary Memoory
- CMain Memory
- DCache Memory
- EVirtual Memory
70Which type of memory stores frequently used data
- ACache Memory
- BAuxiliary Memory
- CMain Memory
- DVirtual Memory
- ESecondary Memory
71Stage in which the instruction is fetched from memory and placed in the instruction register called
- AInstruction Fetch
- BExecution
- CInstruction Decode
- DMemory read/write
- EWrite Back
72Which stage is responsible for storing and loading values to and from memory
- AInstruction Fetch
- BInstruction Decode
- CExecution
- DMemory read/write
- EWrite Back
73Select cache optimizations to reduce hit time (both basic and advanced){
- AAvoiding Address Translation during Cache Indexing
- BSmall and Simple First-Level Caches
- CWay Prediction
- DCompiler Optimizations
- ECompiler-Controlled Prefetching
74Choose the right formula for AMAT</p>{
- AAMAT \= Hit time + Miss rate * Miss penalty
- BAMAT \= Hit time + Miss rate + Miss penalty
- CAMAT \= Hit time * Miss rate + Miss penalty
- DAMAT \= Hit time * Miss rate * Miss penalty
75Select the correct interpretation(s) of Amdahl's Law{
- Ais used to compare computers' performance
- Bis used calculate the execution time of a program
- Cis used to find the maximum expected improvement
- Dit means that it is the algorithm that decides the speedup not the number of processors
76SSD is over 10 times faster than the spinning disks in HDD
- AVerdadero
- BFalso
77SSDs are more susceptible to physical shock and vibration
- AVerdadero
- BFalso
78SSDs are susceptible to mechanical wear
- AVerdadero
- BFalso
79Static RAM has a reduced power consumption, and a large storage capacity
- AVerdadero
- BFalso
80The "natural" unit of organization of memory is called block
- AVerdadero
- BFalso
81The advantage of virtual memory is that it takes less time to switch between applications because of additional memory
- AVerdadero
- BFalso
82The basic element of a semiconductor memory is the memory cell
- AVerdadero
- BFalso
83The execution time of a program clearly depends on the number of instructions
- AVerdadero
- BFalso
84The more clock rate of processor, the faster is processor
- AVerdadero
- BFalso
85The particular block is currently being stored is called tag
- AVerdadero
- BFalso
86The RAID scheme consists of 7 levels
- AVerdadero
- BFalso
87The time interval is called a clock rate
- AVerdadero
- BFalso
88There are three types of cache addresses
- AVerdadero
- BFalso
89There are two types of mapping functions
- AVerdadero
- BFalso
90Three bits make hexadecimal digit
- AVerdadero
- BFalso
91We can find needed block in associatively mapped cache by its block address
- AVerdadero
- BFalso
92Word is the "natural" unit of organization of memory
- AVerdadero
- BFalso
93Static RAM has a reduced power consumption, and a large storage capacity : FALSE
- AVerdadero
- BFalso
94Pipelining can only be implemented on hardware
- AVerdadero
- BFalso
95A technique used in advanced microprocessors where the microprocessor begins executing a first instruction before the second has been completed is called
- AVerdadero
- BFalso
96In execution stage identification of the operation is performed
- AVerdadero
- BFalso
Información
- Descripción
- Test sobre CsaMid1, creado por Nurbol Nazarov el 16/10/2018.
- Autor
- Nurbol Nazarov
- Idioma
- English
- Visitas
- 0
- Valoración
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