Test
final cis126
Crea una cuenta gratis para terminar este test
Guarda tu progreso y consulta tu resultado final.
¿Ya tienes cuenta? Inicia sesión
Preguntas del test (120)
1The basic element of a semiconductor memory is the memory cell.
- AVerdadero
- BFalso
2A characteristic of ROM is that it is volatile.
- AVerdadero
- BFalso
3RAM must be provided with a constant power supply.
- AVerdadero
- BFalso
4The two traditional forms of RAM used in computers are DRAM and SRAM
- AVerdadero
- BFalso
5A static RAM will hold its data as long as power is supplied to it.
- AVerdadero
- BFalso
6Nonvolatile means that power must be continuously supplied to the memory to preserve the
bit values.- AVerdadero
- BFalso
7The advantage of RAM is that the data or program is permanently in main memory and need
never be loaded from a secondary storage device.- AVerdadero
- BFalso
8Semiconductor memory comes in packaged chips.
- AVerdadero
- BFalso
9All DRAMs require a refresh operation.
- AVerdadero
- BFalso
10A number of chips can be grouped together to form a memory bank.
- AVerdadero
- BFalso
11An error-correcting code enhances the reliability of the memory at the cost of added
complexity.- AVerdadero
- BFalso
12DRAM is much costlier than SRAM
- AVerdadero
- BFalso
13Flash memory is only used for internal memory applications
- AVerdadero
- BFalso
14The SDRAM performs best when it is transferring large blocks of data sequentially such as
for word processing, spreadsheets, and multimedia.- AVerdadero
- BFalso
15NOR memory is better suited for external memory such as USB flash drives and memory cards.
- AVerdadero
- BFalso
16Greater ability to withstand shock and damage, improvement in the uniformity of the magnet film
surface to increase disk reliability, and a significant reduction in overall surface defects to help reduce
read-write errors, are all benefits of ___________.- Amagnetic read and write mechanisms
- Bplatters
- Cthe glass substrate
- Da solid state drive
17Adjacent tracks are separated by _________.
- Asectors
- Bgaps
- Cpits
- Dheads
18Data are transferred to and from the disk in __________.
- Atracks
- Bgaps
- Csectors
- Dpits
19 In most contemporary systems fixed-length sectors are used, with _________ bytes being the nearly
universal sector size.- A64
- B128
- C256
- D512
20Scanning information at the same rate by rotating the disk at a fixed speed is known as the
_________.- Aconstant angular velocity
- Bmagnetoresistive
- Crotational delay
- Dconstant linear velocity
21The disadvantage of _________ is that the amount of data that can be stored on the long outer tracks
is only the same as what can be stored on the short inner tracks.- Assd
- Bcav
- Crom
- Dclv
22A __________ disk is permanently mounted in the disk drive, such as the hard disk in a personal
computer- Anonremovable
- Bmovable-head
- Cdouble sided
- Dremovable
23 When the magnetizable coating is applied to both sides of the platter the disk is then referred to as
_________.- Amultiple sided
- Bsubstrate
- Cdouble sided
- Dall the above
24The set of all the tracks in the same relative position on the platter is referred to as a _________.
- Afloppy disk
- Bsingle-sided disk
- Csector
- Dcylinder
25The sum of the seek time and the rotational delay equals the _________, which is the time it takes to
get into position to read or write.- Aaccess time
- Bgap time
- Ctransfer time
- Dconstant angular velocity
26 __________ is the standardized scheme for multiple-disk database design.
- Araid
- Bcav
- Cclv
- Dssd
27RAID level ________ has the highest disk overhead of all RAID types
- A0
- B1
- C3
- D5
28 A _________ is a high-definition video disk that can store 25 Gbytes on a single layer on a single
side.- Advd
- Bdvd-r
- Cdvd-rw
- Dblu-ray dvd
29 ________ is when the disk rotates more slowly for accesses near the outer edge than for those near
the center.- AConstant angular velocity (CAV)
- BMagnetoresistive
- CConstant linear velocity (CLV)
- DSeek time
30The areas between pits are called _________.
- Alands
- Bsectors
- Ccylinders
- Dstrips
31 The __________ is a program that controls the execution of application programs and acts as an
interface between applications and the computer hardware.- Ajob control language
- Boperating system
- Cbatch system
- Dnucleus
32 Facilities and services provided by the OS that assist the programmer in creating programs are in the
form of _________ programs that are not actually part of the OS but are accessible through the OS.- Autility
- Bmultitasking
- CJCL
- Dlogical address
33The _________ defines the repertoire of machine language instructions that a computer can follow.
- Aabi
- Bapi
- Chll
- Disa
34The _________ defines the system call interface to the operating system and the hardware resources
and services available in a system through the user instruction set architecture.- Ahll
- Bapi
- Cabi
- Disa
35The ________ gives a program access to the hardware resources and services available in a system
through the user instruction set architecture supplemented with high-level language library calls.- Ajcl
- Bisa
- Cabi
- Dapi
36A _________ system works only one program at a time.
- Abatch
- Buniprogramming
- Ckernel
- Dprivileged instruction
37A _________ is a special type of programming language used to provide instructions to the monitor.
- Ajob control language
- Bmultiprogram
- Ckernel
- Dutility
38The _________ scheduler determines which programs are admitted to the system for processing.
- Along term
- Bmedium term
- Cshort term
- Di/o
39The ________ scheduler is also known as the dispatcher.
- Along term
- Bmedium term
- Cshort term
- Di/o
40A _________ is an actual location in main memory.
- Alogical address
- Bpartition address
- Cbase address
- Dphysical address
41 ________ is when the processor spends most of its time swapping pages rather than executing
instructions.- Aswaping
- Bthrashing
- Cpaging
- Dmultitasking
42Virtual memory schemes make use of a special cache called a ________ for page table entries.
- Atlb
- Bhll
- Cvmc
- Dspb
43With _________ the virtual address is the same as the physical address.
- Aunsegmented unpaged memory
- Bunsegmented paged memory
- Csegmented unpaged memory
- Dsegmented paged memory
44A _________ is a collection of memory regions.
- Aapx
- Bnucleus
- Cdomain
- Dpage table
45 The OS maintains a __________ for each process that shows the frame location for each page of the
process- Akernel
- Bpage table
- Ctlb
- Dlogical address
46 __________ are a set of storage locations.
- Aprocessors
- BPSWs
- Cregisters
- Dcontrol units
47The ________ controls the movement of data and instructions into and out of the processor.
- Acontrol unit
- Balu
- Cshifter
- Dbranch
48 ________ registers may be used only to hold data and cannot be employed in the calculation of an
operand address.- Ageneral purpose
- Bdata
- Caddress
- Dcondition code
49 __________ are bits set by the processor hardware as the result of operations.
- AMIPS
- Bcondition codes
- Cstacks
- DPSWs
50 The _________ contains the address of an instruction to be fetched.
- Ainstruction register
- Bmemory address register
- Cmemory buffer register
- Dprogram counter
51The _________ contains a word of data to be written to memory or the word most recently read.
- Amar
- Bpc
- Cmbr
- Dir
52 The ________ determines the opcode and the operand specifiers.
- Adecode instruction
- Bfetch operands
- Ccalculate operands
- Dexecute instruction
53_________ is a pipeline hazard.
- Acontrol
- Bresource
- Cdata
- Dall of the above
54A ________ hazard occurs when there is a conflict in the access of an operand location.
- Aresource
- Bdata
- Cstructural
- Dcontrol
55A _________ is a small, very-high-speed memory maintained by the instruction fetch stage of the
pipeline and containing the n most recently fetched instructions in sequence.- Aloop buffer
- Bdelayed branch
- Cmultiple stream
- Dbranch prediction
56The _________ is a small cache memory associated with the instruction fetch stage of the pipeline
- Adynamic branch
- Bloop table
- Cbranch history table
- Dflag
57The _________ stage includes ALU operations, cache access, and register update.
- Adecode
- Bexecute
- Cfetch
- Dwrite back
58 ________ is used for debugging.
- Adirection flag
- Balignment check
- Ctrap flag
- Didentification flag
59The ARM architecture supports _______ execution modes.
- A2
- B8
- C11
- D7
60The OS usually runs in ________.
- Asupervisor mode
- Babort mode
- Cundefined mode
- Dfast interrupt mode
61 _________ determines the control and pipeline organization.
- Acalculation
- Bexecution sequencing
- Coperations performed
- Doperands used
62The Patterson study examined the dynamic behavior of _________ programs, independent of the
underlying architecture.- Ahll
- Brisc
- Ccisc
- Dall of the above
63 _________ is the fastest available storage device.
- Amain memory
- Bcache
- Cregister storage
- Dhll
64The first commercial RISC pro duct was ________
- Asparc
- Bcisc
- Cvax
- Dthe pyramid
65 _________ instructions are used to position quantities in registers temporarily for computational
operations.- Aload and store
- Bwindow
- Ccomplex
- Dbranch
66Which stage is required for load and store operations?
- Ai
- Be
- Cd
- Dall of the above
67A ________ instruction can be used to account for data and branch delays.
- Asub
- Bnoop
- Cjump
- Dall of the above
68The instruction location immediately following the delayed branch is referred to as the ________.
- Adelay load
- Bdelay file
- Cdelay slot
- Ddelay register
69A tactic similar to the delayed branch is the _________, which can be used on LOAD instructions.
- Adelayed load
- Bdelayed program
- Cdelayed slot
- Ddelayed register
70The MIPS R4000 uses ________ bits for all internal and external data paths and for addresses,
registers, and the ALU.- A16
- B32
- C64
- D128
71All MIPS R series processor instructions are encoded in a single ________ word format.
- A4 bit
- B8 bit
- C16 bit
- D32 bit
72A _________ architecture is one that makes use of more, and more fine-grained pipeline stages.
- Aparallel
- Bsuperpipelined
- Csuperscalar
- Dhybrid
73The R4000 can have as many as _______ instructions in the pipeline at the same time.
- A8
- B10
- C5
- D3
74 SPARC refers to an architecture defined by _______
- Amicrosoft
- Bapple
- Csun microsystems
- Dibm
75The R4000 pipeline stage where the instruction result is written back to the register file is the
__________ stage.- Awrite back
- Btag check
- Cdata chache
- Dinstruction execute
76The superscalar approach has now become the standard method for implementing
highperformance microprocessors.- AVerdadero
- BFalso
77In a traditional scalar organization there is a single pipelined functional unit for integer
operations and one for floating-point operations.- AVerdadero
- BFalso
78In the scalar organization there are multiple functional units, each of which is implemented
as a pipeline and provides a degree of parallelism by virtue of its pipelined structure.- AVerdadero
- BFalso
79The superscalar approach depends on the ability to execute multiple instructions in parallel.
- AVerdadero
- BFalso
80True data dependency is also called flow dependency or read after write (RAW) dependency.
- AVerdadero
- BFalso
81Resources include: memories, caches, buses, and register-file ports
- AVerdadero
- BFalso
82Machine parallelism exists when instructions in a sequence are independent and thus can be
executed in parallel by overlapping.- AVerdadero
- BFalso
83The simplest instruction issue policy is to issue instructions in the exact order that would be
achieved by sequential execution (in-order issue) and to write results in that same order (in-order
completion).- AVerdadero
- BFalso
84In-order completion requires more complex instruction issue logic than out-of-order
completion.- AVerdadero
- BFalso
85The reorder buffer is temporary storage for results completed out of order that are then
committed to the register file in program order.- AVerdadero
- BFalso
86Register renaming eliminates antidependencies and output dependencies.
- AVerdadero
- BFalso
87In effect, the Intel Core architecture implements a CISC instruction set architecture on a
RISC microarchitecture.- AVerdadero
- BFalso
88The schedulers are responsible for retrieving micro-ops from the micro-op queues and
dispatching these for execution.- AVerdadero
- BFalso
89ARM architecture has yet to implement superscalar techniques in the instruction pipeline.
- AVerdadero
- BFalso
90The Cortex-A8 targets a wide variety of mobile andconsumer applications including mobile
phones, set-top boxes, gaming consoles and automotives navigation/entertainment systems.- AVerdadero
- BFalso
91Symmetric multiprocessors (SMPs) are one of the earliest, and still the most common,
example of parallel organization.- AVerdadero
- BFalso
92The term SMP refers to a computer hardware architecture and also to the operating system
behavior that reflects that architecture.- AVerdadero
- BFalso
93An attractive feature of an SMP is that the existence of multiple processors is transparent to
the user.- AVerdadero
- BFalso
94The main drawback of the bus organization is reliability.
- AVerdadero
- BFalso
95An SMP operating system manages processor and other computer resources so that the user
perceives a single operating system controlling system resources.- AVerdadero
- BFalso
96Software cache coherence schemes attempt to avoid the need for additional hardware
circuitry and logic by relying on the compiler and operating system to deal with the problem.- AVerdadero
- BFalso
97Snoopy protocols are not suitable for a bus-based multiprocessor.
- AVerdadero
- BFalso
98With a write-update protocol there can be multiple readers but only one writer at a time.
- AVerdadero
- BFalso
99An L1 cache that does not connect directly to the bus cannot engage in a snoopy protocol
- AVerdadero
- BFalso
100The most important measure of performance for a processor is the rate at which it executes
instructions.- AVerdadero
- BFalso
101 With multithreading the instruction stream is divided into several smaller streams, known as
threads, such that the threads can be executed in parallel.- AVerdadero
- BFalso
102The function of switching applications and data resources over from a failed system to an
alternative system in the cluster is referred to as failback.- AVerdadero
- BFalso
103Both clusters and symmetric multiprocessors provide a configuration with multiple
processors to support high-demand applications.- AVerdadero
- BFalso
104The objective with NUMA is to maintain a transparent system wide memory while
permitting multiple multiprocessor nodes, each with its own bus or other internal interconnect system.- AVerdadero
- BFalso
105A cloud broker is useful when cloud services are too complex for a cloud consumer to easily
manage- AVerdadero
- BFalso
106The organizational changes in processor design have primarily been focused on increasing
instruction-level parallelism so that more work could be done in each clock cycle.- AVerdadero
- BFalso
107With superscalar organization increased performance can be achieved by increasing the
number of parallel pipelines.- AVerdadero
- BFalso
108The increasingly difficult engineering challenge related to processor logic is one of the reasons that
an increasing fraction of the processor chip is devote to the simpler memory logic.- AVerdadero
- BFalso
109The demand on power requirements has not grown as chip density and clock frequency have risen.
- AVerdadero
- BFalso
110As chip transistor density has increased, the percentage of chip area devoted to memory has
decreased.- AVerdadero
- BFalso
111The potential performance benefits of a multicore organization depend on the ability to
effectively exploit the parallel resources available to the application.- AVerdadero
- BFalso
112Database management systems and database applications are one area in which multicore
systems can be used effectively- AVerdadero
- BFalso
113Even if an individual application does not scale to take advantage of a large number of
threads, it is still possible to gain from multicore architecture by running multiple instances of the
application in parallel.- AVerdadero
- BFalso
114With hybrid threading each major module is single threaded and the principal coordination
involves synchronizing all the threads with a timeline thread.- AVerdadero
- BFalso
115The ARM11 MPCore is an example of the L1 cache being divided into instruction and data
caches- AVerdadero
- BFalso
116An advantage of using a shared L2 cache on the chip is that data shared by multiple cores is
not replicated at the shared cache level.- AVerdadero
- BFalso
117A potential advantage to having only dedicate L2 caches on the chip is that each core enjoys
more rapid access to its private L2 cache.- AVerdadero
- BFalso
118The big.Little architecture uses a combination of ARM Cortex-A7 and Cortex A-15 cores.
- AVerdadero
- BFalso
119The generic timer handles interrupt detection and interrupt prioritization.
- AVerdadero
- BFalso
120Direct data intervention enables copying clean data from one CPU L1 data cache to another CPU
L1 data cache without accessing external memory.- AVerdadero
- BFalso
Información
- Descripción
- Test sobre final cis126, creado por ron pisechko el 09/12/2018.
- Autor
- ron pisechko
- Idioma
- English
- Visitas
- 13
- Valoración
- Aún sin valoraciones Valora este test