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Preguntas del test (162)
1Associative Mapping
- AEach block mapped to any cache location
- BEach memory block is mapped to exactly one block in the cache
- CEach block mapped to subset of cache locations
2Direct Mapping
- AEach block mapped to any cache location
- BEach memory block is mapped to exactly one block in the cache
- CEach block mapped to subset of cache locations
3Set-Associative Mapping
- AEach block mapped to any cache location
- BEach memory block is mapped to exactly one block in the cache
- CEach block mapped to subset of cache locations
4Structural hazardsВ
- Adifferent instructions in different stages (or the same stage) conflicting for the same resource
- Ban instruction cannot continue because it needs a value that has not yet been generated by an earlier instruction
- Cfetch cannot continue because it does not know the outcome of an earlier branch – special case of a data hazard
5Data hazards
- Adifferent instructions in different stages (or the same stage) conflicting for the same resource
- Ban instruction cannot continue because it needs a value that has not yet been generated by an earlier instruction
- Cfetch cannot continue because it does not know the outcome of an earlier branch – special case of a data hazard
6Control hazards
- Adifferent instructions in different stages (or the same stage) conflicting for the same resource
- Ban instruction cannot continue because it needs a value that has not yet been generated by an earlier instruction
- Cfetch cannot continue because it does not know the outcome of an earlier branch – special case of a data hazard
7Compulsory misses
- AThe very first access to a block cannot be in the cache
- BOccurs if the cache cannot contain all the blocks needed during execution of a program
- COccurs if the block placement strategy is not fully associative
8Capaciy misses
- AOccurs if the cache cannot contain all the blocks needed during execution of a program
- BThe very first access to a block cannot be in the cache
- COccurs if the block placement strategy is not fully associative
9Conflict misses
- AOccurs if the block placement strategy is not fully associative
- BOccurs if the cache cannot contain all the blocks needed during execution of a program
- CThe very first access to a block cannot be in the cache
10Choose the feature(s) of first generation computer architecture :
- AVacuum tubes, Assembly language
- BMagnetic core memory, Assembly language
- CTransistors, High level languages
- DUse of cache memory, Semiconductor memory
11A common measure of performance for a processor is the rate at which instructions are executed, called
- ACPI
- BClock Rate
- CMFLOPS
- DMIPS
12A technique used in advanced microprocessors where the microprocessor begins executing a first instruction before the second has been completed is called pipelining
- ATrue
- BFalse
13Choose the features of third generation computer architecture
- AObject-Oriented Programming
- BGraphics
- CTimesharing
- DFloating point arithmetic
- EUse of cache memory
14Choose advanced cache optimizations
- AGiving Reads Priority over Writes
- BHardware Prefetching of Instructions and Data
- CLarger Cache Size
- DMerging Write Buffer
- ECritical Word First and Early Restart
15Choose basic cache optimizations
- ACompiler-Controlled Prefetching
- BNonblocking Caches
- CSmall and Simple First-Level Caches
- DMultilevel Caches
- EAvoiding Address Translation during Cache Indexing
16Choose data dependences
- ARead-After-Read
- BRead-After-Write
- CWrite-After-Write
- DWrite-After-Read
17Choose hazard for the following definition\: an instruction cannot continue because it needs a value that has not yet been generated by an earlier instruction
- AData
- BStructural
- CControl
18Choose hazard for the following definition\: different instructions in different stages (or the same stage) conflicting for the same resource
- AStructural
- BData
- CControl
19Choose hazard for the following definition\: fetch cannot continue because it does not know the outcome of an earlier branch - special case of a data hazard
- AControl
- BStructural
- CData
20Choose the access method(s)
- AParallel Access
- BIndirect Access
- CRandom Access
- DDirect Access
- ESequential Access
21Choose the component of SSD for the following definition\: High speed RAM memory components used for speed matching and to increased data throughput
- AData buffer/cache
- BFlash Memory Components
- CAddressing
- DController
- EError Correction
22Choose the component of SSD for the following definition\: Individual NAND flash chips
- AFlash Memory Components
- BAddressing
- CData buffer/cache
- DController
- EError Correction
23Choose the component of SSD for the following definition\: Logic for error detection and correction
- AError Correction
- BAddressing
- CData buffer/cache
- DController
- EFlash memory components
24Choose the component of SSD for the following definition\: Logic that performs the selection function across the flash memory components
- AAddressing
- BFlash Memory Components
- CData buffer/cache
- DController
- EError Correction
25Choose the component of SSD for the following definition\: provides SSD device level interfacing and firmware execution
- AController
- BAddressing
- CData buffer/cache
- DError correction
- EFlash memory components
26Choose the definition for capacity misses
- AOccurs if the cache cannot contain all the blocks needed during execution of a program
- BThe very first access to a block cannot be in the cache
- COccurs if the block placement strategy is not fully associative
27Choose the components of SSD
- AController
- BAddressing
- CData buffer/cache
- DData size
- EMemory hierarchy
28Choose the definition for compulsory misses
- AOccurs if the cache cannot contain all the blocks needed during execution of a program
- BOccurs if the block placement strategy is not fully associative
- CThe very first access to a block cannot be in the cache
29Choose the definition for conflict misses
- AOccurs if the block placement strategy is not fully associative
- BOccurs if the cache cannot contain all the blocks needed during execution of a program
- CThe very first access to a block cannot be in the cache
30Choose the element(s) of cache design
- ATag
- BLatency
- CAMAT
- DMapping Function
- EReplacement Algorithm
- FNumber of Caches
31Choose the element(s) of cache design
- ATag
- BLatency
- CAMAT
- DCache Size
- ELine Size
- FNumber of Caches
32Choose the feature(s) of first generation computer architecture
- AMagnetic core memory
- BSemiconductor memory
- CMachine code
- DVacuum tubes
- EAssembly language
33Choose the feature(s) of fourth generation computer architecture
- AObject-Oriented programming
- BWide spread use of data communications
- CSmallest in size
- DUse of cache memory
- EUse of drum memory or magnetic core memory
34Choose the feature(s) of second generation computer architecture
- AHigh level languages
- BTransistors
- C2 Kb memory, 10 KIPS
- D2 Mb memory, 5 MIPS
- EDifferent types of supported instructions
35Choose the feature(s) of third generation computer architecture
- AObject-Oriented programming
- BFloating point arithmetic
- CGraphics
- DTimesharing
- EUse of cache memory
36Choose the key characteristics of computer memory systems
- APhysical Type
- BPhysical Characteristics
- CAccess Method
- DUnit of Transfer
- EPerformance
37Choose the key characteristics of computer memory systems
- ALocation
- BUnit of Transfer
- CAccess Method
- DStalling
- EHazards
38Choose the key characteristics of computer memory systems
- ACapacity
- BPerformance
- COrganization
- DInstruction Fetch
- EInstruction Decode
39Choose the performance factor(s)
- ACache Size
- BLine Size
- CInstruction Count
- DNumber of Processor Cycles
- ENumber of memory references
40Choose the physical characteristic(s) of disk systems
- ADisk system implementstion
- BDisk Size
- CHead Mechanism
- DPlatters
- ESides
41Choose the physical characteristic(s) of disk systems
- ADisk system implementstion
- BDisk Size
- CHead Mechanism
- DHead Motion
- EDisk Portability
42Choose the system attribute(s) by which the performance factors are influenced
- ACache size
- BUnit of Transfer
- CCompiler Technology
- DProcessor Implementation
- ECache and memory hierarchy
43Choose the type(s) of auxiliary memory
- AFlash Memory
- BOptical Disk
- CHard Drive
- DSSD
- ERAM
44Choose the years of the first generation computer architecture
- A1958-1964
- B1964-1974
- C1974-present
- D1945-1964
- E1945-1958
45Choose the years of the second generation computer architecture
- A1945-1958
- B1964-1974
- C1974-present
- D1945-1964
- E1958-1964
46Choose two types of models for a computing machine
- AHarvard architecture
- BVon Neumann architecture
- COxford architecture
- DStanford architecture
47CPU Time \= I * CPI / R. Which parameter requires special profiling software?
- ACycles Per instruction
- BClock Rate
- CNumbers of instructions
- DExecution time
48Floating point performance is expressed as
- ACPI
- BFLOPS
- CMIPS
- DMFLOPS
49For random-access memory, the time it takes to perform a read or write operation is called
- AClock Rate
- BCPI
- CAccess Time
- DLatency
50Four bits make octal digit
- AVerdadero
- BFalso
51Four bits make octal digit
- AVerdadero
- BFalso
52Halting the flow of instructions until the required result is ready to be used is called
- Awaiting
- Bdelaying
- Chalting
- Dstalling
53How a binary digit is called?
- Abyte
- Bdigit
- Ckilobyte
- Dbit
54How a memory unit accessed by contents is called?
- AAssociative Memory
- BContent Addressable Memory
- CAuxiliary Memory
- DCache Memory
- EVirtual Memory
55How external nonvolatile memory is called?
- ASecondary memory
- BMain memory
- CCache memory
- DVirtual memory
56How many access methods are there?
- A3
- B2
- C4
- D5
- E6
57How many elements of cache design are there?
- A2
- B5
- C4
- D6
- E7
58How many generations of computer architecture are there?
- A4
- B3
- C2
- D1
- E5
59How many number systems are there?
- A1
- B2
- C3
- D4
60How many performance factors are there
- A5
- B4
- C3
- D2
- E6
61How many physical characteristics of disk systems are there?
- A4
- B5
- C2
- D3
- E6
62How the stage in which the results of the operation are written to the destination register is called?
- AInstruction Fetch
- BWrite Back
- CInstruction Decode
- DExecution
- EMemory read/write
63IBM System/360 Model 91 was introduced in 1966
- AVerdadero
- BFalso
64In 1976 Apple II computer model was released
- AVerdadero
- BFalso
65In execution stage identification of the operation is performed
- AVerdadero
- BFalso
66In LRU replacement algorithm, the block that is in the cache longest is replaced
- AVerdadero
- BFalso
67In virtual memory, memory can be used efficiently because a section of program always loaded
- AVerdadero
- BFalso
68In which cache memory mapping technique any block from main memory can be placed anywhere in the cache?
- AAssociative Mapping
- BSet Associative Mapping
- CDirect Mapping
69In which cache memory mapping technique any memory block is mapped to exactly one block in the cache?
- ADirect Mapping
- BSet Associative Mapping
- CAssociative Mapping
70In which cache memory mapping technique any memory block mapped to subset of cache locations?
- ASet Associative Mapping
- BDirect Mapping
- CAssociative Mapping
71Into how many parts a program (or algorithm) which can be parallelized can be split up?
- A3
- B4
- C5
- D2
72Select cache optimizations to reduce miss penalty
- AMultilevel Caches
- BGiving Reads Priority over Writes
- CHigher associativityВ
- DWay Prediction
73Select cache optimizations to increase the Cache Bandwidth
- ANonblocking Caches
- BMultibanked Caches
- CSmall and Simple First-Level Caches
- DMultilevel Caches
- EPipelined Cache Access
74Select cache optimizations to reduce miss penalty
- AMultilevel Caches
- BGiving Reads Priority over Writes
- CHigher associativityВ
- DWay Prediction
75Octal and hexadecimal numbers are hard on use and conversion
- AVerdadero
- BFalso
76Physical address used by program, and which OS must translate into virtual address
- AVerdadero
- BFalso
77Pipelining can only be implemented on hardware
- AVerdadero
- BFalso
78Process of instruction execution is divided into two or more steps, called
- Apipelining
- Bpipe stages
- Cpipe segments
- Dinstruction execution
- Epipeline hazard
79ROM is the place in a computer where the operating system, application programs, and data in current use are kept.
- AVerdadero
- BFalso
80Choose the features of first generation computer architecture
- AVacuum tubes
- BAssembly language
- CMagnetic core memory
- DSemiconductor memory
- EMachine code
81How aВ memory unit accessed by contents is called?
- AAssociative Memory
- BContent Addressable Memory
- CAuxiliary Memory
- DCache Memory
- EVirtual Memory
82Choose the access methods
- ARandom Access
- BParallel Access
- CSequential Access
- DIndirect Access
- EDirect Access
83In which cache memory mapping techniqueВ any block from main memory can be placed anywhere in the cache?
- AAssociative Mapping
- BSet Associative Mapping
- CDirect Mapping
84Choose the features of first generation computer architecture
- AVacuum tubes
- BAssembly language
- CMagnetic core memory
- DSemiconductor memory
- EMachine code
85Which type of memoryВ accessed via the input/output channels?
- AAuxiliary Memory
- BSecondary Memoory
- CMain Memory
- DCache Memory
- EVirtual Memory
86Which type of memory stores frequently used data?
- ACache Memory
- BAuxiliary Memory
- CMain Memory
- DVirtual Memory
- ESecondary Memory
87How aВ memory unit accessed by contents is called?
- AAssociative Memory
- BContent Addressable Memory
- CAuxiliary Memory
- DCache Memory
- EVirtual Memory
88Which type of memory stores frequently used data?
- ACache Memory
- BAuxiliary Memory
- CMain Memory
- DVirtual Memory
- ESecondary Memory
89Choose the access methods
- ARandom Access
- BParallel Access
- CSequential Access
- DIndirect Access
- EDirect Access
90In which cache memory mapping technique any block from main memory can be placed anywhere in the cache?
- AAssociative Mapping
- BSet Associative Mapping
- CDirect Mapping
91Which type of memory accessed via the input/output channels?
- AAuxiliary Memory
- BSecondary Memoory
- CMain Memory
- DCache Memory
- EVirtual Memory
92Process of instruction execution is divided into two or more steps, called
- Apipe stages
- Bpipe segments
- Cpipelining
- Dinstruction execution
- Epipeline hazard
93Process of instruction execution is divided into two or more steps, called
- Apipe stages
- Bpipe segments
- Cpipelining
- Dinstruction execution
- Epipeline hazard
94Stage in which the instruction is fetched from memory and placed in the instruction register called
- AInstruction Fetch
- BInstruction Decode
- CExecution
- DMemory read/write
- EWrite Back
95Which stage is responsible for storing and loading values to and from memory?
- AInstruction Fetch
- BInstruction Decode
- CExecution
- DMemory read/write
- EWrite Back
96Stage in which the instruction is fetched from memory and placed in the instruction register called
- AInstruction Fetch
- BInstruction Decode
- CExecution
- DMemory read/write
- EWrite Back
97How the stage in which the results of the operation are written to the destination register is called?
- AInstruction Fetch
- BInstruction Decode
- CExecution
- DMemory read/write
- EWrite Back
98Which stage is responsible for storing and loading values to and from memory?
- AInstruction Fetch
- BInstruction Decode
- CExecution
- DMemory read/write
- EWrite Back
99How the stage in which the results of the operation are written to the destination register is called?
- AInstruction Fetch
- BInstruction Decode
- CExecution
- DMemory read/write
- EWrite Back
100Choose advanced cache optimizations
- AHardware Prefetching of Instructions and Data
- BMerging Write Buffer
- CGiving Reads Priority over Writes
- DLarger Cache Size
- ECritical Word First and Early Restart
101Select cache optimizations to reduce hit time (both basic and advanced)
- AAvoiding Address Translation during Cache Indexing
- BSmall and Simple First-Level Caches
- CWay Prediction
- DCompiler Optimizations
- ECompiler-Controlled Prefetching
102Choose the right formula for AMAT
- AAMAT \= Hit time + Miss rate * Miss penalty
- BAMAT \= Hit time + Miss rate + Miss penalty
- CAMAT \= Hit time * Miss rate + Miss penalty
- DAMAT \= Hit time * Miss rate * Miss penalty
103Choose basic cache optimizations
- ACompiler-Controlled Prefetching
- BNonblocking Caches
- CMultilevel Caches
- DAvoiding Address Translation during Cache Indexing
- ESmall and Simple First-Level Caches
104Choose advanced cache optimizations
- AHardware Prefetching of Instructions and Data
- BMerging Write Buffer
- CGiving Reads Priority over Writes
- DLarger Cache Size
- ECritical Word First and Early Restart
105Select cache optimizations to reduce hit time (both basic and advanced)
- AAvoiding Address Translation during Cache Indexing
- BSmall and Simple First-Level Caches
- CWay Prediction
- DCompiler Optimizations
- ECompiler-Controlled Prefetching
106Select cache optimizations to increase the Cache Bandwidth
- ANonblocking Caches
- BMultibanked Caches
- CPipelined Cache Access
- DMultilevel Caches
- ESmall and Simple First-Level Caches
107Select cache optimizations to reduce hit time (both basic and advanced)
- AAvoiding Address Translation during Cache Indexing
- BSmall and Simple First-Level Caches
- CWay Prediction
- DCompiler Optimizations
- ECompiler-Controlled Prefetching
108Select cache optimizations to reduce miss penalty
- AMultilevel Caches
- BGiving Reads Priority over Writes
- CWay Prediction
- DHigher associativity
109Select the correct interpretation(s) of Amdahl's Law
- Ais used to compare computers' performance
- Bis used calculate the execution time of a program
- Cis used to find the maximum expected improvement
- Dit means that it is the algorithm that decides the speedup not the number of processors
110SSD is over 10 times faster than the spinning disks in HDD
- AVerdadero
- BFalso
111SSD stands for : Solid State Drive
- AVerdadero
- BFalso
112SSDs are more susceptible to physical shock and vibration
- AVerdadero
- BFalso
113SSDs are susceptible to mechanical wear
- AVerdadero
- BFalso
114Stage in which the instruction is fetched from memory and placed in the instruction register called : Instruction Fetch
- AVerdadero
- BFalso
115Static RAM has a reduced power consumption, and a large storage capacity
- AVerdadero
- BFalso
116The "natural" unit of organization of memory is called block
- AVerdadero
- BFalso
117The advantage of virtual memory is that it takes less time to switch between applications because of additional memory
- AVerdadero
- BFalso
118The basic element of a semiconductor memory is the memory cell
- AVerdadero
- BFalso
119The execution time of a program clearly depends on the number of instructions
- AVerdadero
- BFalso
120The more clock rate of processor, the faster is processor
- AVerdadero
- BFalso
121The particular block is currently being stored is called tag
- AVerdadero
- BFalso
122The RAID scheme consists of 7 levels
- AVerdadero
- BFalso
123The rate at which data can be transferred into or out of a memory unit is called::[html]The rate at which data can be transferred into or out of a memory unit is called : Transfer Rate
- AVerdadero
- BFalso
124The time interval is called a clock rate
- AVerdadero
- BFalso
125There are three types of cache addresses
- AVerdadero
- BFalso
126There are two types of mapping functions
- AVerdadero
- BFalso
127Three bits make hexadecimal digit
- AVerdadero
- BFalso
128We can find needed block in associatively mapped cache by its block address
- AVerdadero
- BFalso
129What does CPI stand for? : Cycles Per Instruction
- AVerdadero
- BFalso
130What does LRU stand for? : Least Recently Used
- AVerdadero
- BFalso
131What does RAID stand for : Redundant Array of Independent Disks
- AVerdadero
- BFalso
132What is included into performance characteristic of computer memory systems? : Access time, Cycle Time, Transfer Rate
- AVerdadero
- BFalso
133What is included into physical type characteristic of computer memory systems? : Semiconductor, Magnetic
- AVerdadero
- BFalso
134What is time elapsed to program execution? : CPU Time + I/O waiting & Other programs
- AVerdadero
- BFalso
135Which digits are used in octal number system? : 0-7
- AVerdadero
- BFalso
136Which stage is responsible for storing and loading values to and from memory? Memory read/write
- AVerdadero
- BFalso
137Which type of memory accessed via the input/output channels : Auxiliary Memory, Secondary Memory
- AVerdadero
- BFalso
138Which type of memory stores frequently used data : Cache Memory
- AVerdadero
- BFalso
139Word is the "natural" unit of organization of memory
- AVerdadero
- BFalso
140What does LRU stand for? Answer format\: Aaa Bbb Ccc : Least Recently Used
- AVerdadero
- BFalso
141Halting the flow of instructions until the required result is ready to be used is called : stalling
- AVerdadero
- BFalso
142Static RAM has a reduced power consumption, and a large storage capacity
- AVerdadero
- BFalso
143ROM is the place in a computer where the operating system, application programs, and data in current use are kept
- AVerdadero
- BFalso
144In LRU replacement algorithm, the block that is in the cache longest is replaced
- AVerdadero
- BFalso
145ROM is the place in a computer where the operating system, application programs, and data in current use are kept
- AVerdadero
- BFalso
146In LRU replacement algorithm, the block that is in the cache longest is replaced
- AVerdadero
- BFalso
147Static RAM has a reduced power consumption, and a large storage capacity
- AVerdadero
- BFalso
148ROM is the place in a computer where the operating system, application programs, and data in current use are kept
- AVerdadero
- BFalso
149In LRU replacement algorithm, the block that is in the cache longest is replaced
- AVerdadero
- BFalso
150Pipelining can only be implemented on hardware
- AVerdadero
- BFalso
151A technique used in advanced microprocessors where the microprocessor begins executing a first instruction before the second has been completed is called
- AVerdadero
- BFalso
152In execution stage identification of the operation is performed
- AVerdadero
- BFalso
153Pipelining can only be implemented on hardware
- AVerdadero
- BFalso
154A technique used in advanced microprocessors where the microprocessor begins executing a first instruction before the second has been completed is called
- AVerdadero
- BFalso
155In execution stage identification of the operation is performed
- AVerdadero
- BFalso
156In virtual memory, memory can be used efficiently because a section of program always loaded
- AVerdadero
- BFalso
157The advantage of virtual memory is that it takes less time to switch between applications because of additional memory
- AVerdadero
- BFalso
158Physical address used by program, and which OS must translate into virtual address
- AVerdadero
- BFalso
159In virtual memory, memory can be used efficiently because a section of program always loaded
- AVerdadero
- BFalso
160The advantage of virtual memory is that it takes less time to switch between applications because of additional memory
- AVerdadero
- BFalso
161Physical address used by program, and which OS must translate into virtual address
- AVerdadero
- BFalso
162Choose the key characteristics of computer memory systems
- APhysical Type
- BPhysical Characteristics
- CAccess Method
- DUnit of Transfer
- EPerformance
Información
- Descripción
- Test sobre sabin, creado por Максат Аскер el 16/03/2019.
- Autor
- Максат Аскер
- Idioma
- English
- Visitas
- 13
- Valoración
- Aún sin valoraciones Valora este test