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Untitled1
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Preguntas del test (97)
1Match the computer systems generations:
- AFirst generation
1945-1958 - BSecond generation
1958-1964 - CThird generation
1964-1974 - DFourth generation
1974 – present
- AFirst generation
2Controls the operation of the computer and performs its data processing functions:
- AMain memory
- BI/O
- CCPU
- DSystem interconnection
3The figure reveals that both the control unit and the ALU contain storage, called registers, match the definitions: (her poimi kak dobavit kartinku)
- AContains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit.
Memory buffer register (MBR) - BSpecifies the address in memory of the word to be written from or read into the MBR.
Memory address register (MAR) - CContains the 8-bit opcode instruction being executed.
Instruction register (IR) - DEmployed to hold temporarily the right-hand instruction from a word in memory.
Instruction buffer register (IBR) - EContains the address of the next instruction pair to be fetched from memory.
Program counter (PC)
- AContains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit.
4How the central termination point for data channels, the CPU, and memory is called. It schedules access to the memory from the CPU and data channels, allowing these devices to act independently.
- ATransistor
- BMultiplexor
- CIntegrated circuit
- DResistors
- ECapacitors
5Expand the abbreviation VLSI
- AVery-large-scale integration
- BVery-little-scale integration
- CVery-large-scale interactions
- DVery-large-scale integrator
6Which technique allows to processor simultaneously work on multiple instructions?
- ABranch prediction
- BData flow analysis
- CPipelining
- DSpeculative execution
7Using this technique processor looks ahead in the instruction code fetched from memory and predicts which groups of instructions are likely to be processed next.
- ABranch prediction
- BData flow analysis
- CPipelining
- DSpeculative executions
8Which technique helps to processor investigates which instructions are dependent on each other’s results, or data, to create an optimized schedule of instructions
- ABranch prediction
- BData flow analysis
- CPipelining
- DSpeculative executionss
9This technique enables the processor to keep its execution engines as busy as possible by executing instructions that are likely to be needed.
- ABranch prediction
- BData flow analysis
- CPipelining
- DSpeculative execution
10The world’s first general-purpose microprocessor. It was used in the first personal computer, the Altair.
- A8070
- B8080
- C8086dassad
- D8090
11Which of the following laws deals with the potential speedup of a program using multiple processors compared to a single processor.
- AMoor’s Law
- BLittle’s Laww
- CMurphy's laww
- DAmdahl’s law
1212 .Match the letters with the right name of the Computer Components: Top-Level View:
(tut kartinka)
- AA
IR -Instruction register - BB
MAR-Memory address registers - CC
I/O Input/output address register - DD
I/O Modulee - EE
Main memoryy
- AA
13The processor responds by suspending operation of the current program, branching off to a program to service that particular I/O device, known as _________________, and resuming the original execution after the device is serviced. Which of the following will be the missing word:
- Aiterrupt handler
- Binterrupt cycle
- Cdisabled interrupt
- Dinterruptt request
14What is the data line?
provide a path for moving data among system modules- Aprovide a path for moving data among system modules
- Bis used to designate the source or destination of the data on the data bus
- Ci used to control the access to and the use of the data and address lines
- Dindicates that a module needs to gain control of the bus
15 What is used to manage the access to and the use of the data and address lines?
- Aaddress bus
- Bcontrol lines
- Cmemory write
- Dbus grant
- Eaddress lines
16Bus lines can be separated into two generic types:
- ADedicated, Multiplexed
- BCentralized
- CDistributed
- DMultiplexed
- ESynchronos
- FAsynchronous
17PCI stands for:
- APower Control Interface
- BPeripheral component interconnect
- CProperty Casualty Insurers
- DProgrammable Communications Interface
18The methods of accessing units of data:(multi question)
- ASequential accesss
- BPseudo accesss
- CDirect accesss
- DIndirect accesss
- ESingle accesss
- FRandom accesss
- GAssociative accesss
19match(mul ti q)
- AA
Processorr - BB
Cachee - CC
Dataa - DD
Addresss - EE
Address bufferr - FF
Data bufferr
- AA
20What kind of memory type stores data using virtual addresses:
- ALogicall
- BVirtuall
- CPeripherall
- DMainn
- EBufferr
21Amdahl’s law:
- ASpeed up= 1/(1 + f ) * f/N.
- BSpeed up= 1/(1 - f ) * f/N.
- CSpeed up= 1/(1 - f ) - f/N.
- DSpeed up= 1/(1 - f ) + f/N.
- ESpeed up= 1/(1 + f ) + f/N.
22AMAT stands for:
- AAverage memory access time.
- BAutomatic Message Accounting Transmitter.
- CAsymptotic Mean Acquisition Time.
- DAbsolute memory access time.
23_____________ is a special purpose system that is used to perform one or few dedicated functions.
- ADistributed systems.
- BEmbedded systems.
- CUltra-Large-Scale Systems.
- DCentralized systems.
- EUbiquitous systems.
24Match the statements with the right architecture(multi q)
- AVon Neumann
One memory for data and program, with one bus for both. - BVon Neumann
CPU provides address to get data or instructions. - CVon Neumann
Data and instructions must have the same width. - DHarvard
Separate program and data memories and separate busses, can be accessed simultaneously. - EHarvard
Separated buses allow one instruction to execute while the next instruction is fetched. - FHarvard
Data and instructions mustn’t have the same width.
- AVon Neumann
25How many generations semiconductor memory has been through, since 1970? (please write number)
- A13.
- B12.
- C11.
- D14.
- E10.
26MIC stands for:
- Amini integrated core.
- Bmany integrated core.
- Cmain integrated core.
- Dmany interaction core.
- Emain interaction core.
27Clock Frequency of SDRAM is equal to:
- A200.
- B600.
- C300.
- D166.
- E156.
28An instruction pipeline increases the performance of a processor by overlapping the processing of several different instructions. How many stages it is consist of:
- A6
- B3
- C5
- D7
- E4
29There are three types of hazards that can happen while pipelined execution. Match the hazards with their definitions:(multi q)
- AStructural hazards
different instructions in different stages (or the same stage) conflicting for the same resource. - BData hazards
an instruction cannot continue because it needs a value that has not yet been generated by an earlier instruction. - CControl hazards
fetch cannot continue because it does not know the outcome of an earlier branch – special case of a data hazard.
- AStructural hazards
30_____________ is the amount of time it takes the program to perform in seconds
- AElapsed time.
- BOverall time.
- CEstimate time.
- Dexecution time.
- EProcess time.
31How many number systems are exist?
- A4
- B3
- C2
- D1
32Basic memory elements hold only two states: Zero / One
- ATrue.
- BFalse.
33Which of the following is the right result for this operation: 11001+110001=
- A10101010.
- B10101110.
- C01001010.
- D01100110.
- E10001010
34Convert decimal 230 to the binary:
011000110
011100110
101100110
011100110- A011000110.
- B011100110.
- C101100110.
- D011100110. (same) lol
35Convert binary 1100111 to decimal:
- A103.
- B100.
- C95.
- D130.
- E110.
36A single, self-contained transistor is called ________.
- Aintegrated circuit.
- Bmicrochip.
- Cdiscrete component.
- Dsingle transistor.
- Esmall-scale integration.
37GPU stands for:
- Agraphical processing unit.
- Bgraphical performing units.
- Cgraphics processing units.
- Dgraphics processing utility.
38What measures the ability of a computer to complete a single task?
- AClock rate
- BSpeed metric
- CClock speed.
- DClock cycle.
- EExecution speed.
39Convert hexadecimal value: DAD to decimal:
- A3500.
- B3501.
- C4501.
- D4500.
- E3503.
40Convert decimal value: 877 to hexadecimal:
- A36D.
- B38A.
- C36B.
- D38C.
- E36A.
41How we call the thing that is connects major computer components (processor, memory, I/O)?
- ASystem connector.
- BSystem controllers.
- CSystem bus.
- DSystem interconnector.
42Match the three performance parameters with their definitions. (multi q)
- AAccess time (latency)
This is the time it takes to perform a read or write operation, that is, the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use. - BMemory cycle time
This concept is primarily applied to random-access memory and consists of the access time plus any additional time required before a second access can commence. - CTransfer rate
This is the measurement at which data can be transferred into or out of a memory unit.
- AAccess time (latency)
43Which of the following is the result of the binary multiplication: 100010*100101=
11011101010
10111101010
10010001010
10010101010
10011101010- A11011101010.
- B10111101010.
- C10010001010.
- D10010101010.
- E10011101010.
44Convert the binary value: 111011 to decimal
- A59.
- B58.
- C56
- D60
- E69.
45DRAM stands for:
- ADirect random access memory.
- BDynamic random accessible memory.
- CDynamical random access memory.
- DDynamic random access memory.
- EDiscrete random access memory.
46How is called the permanent physical defect when the memory cell or cells affected cannot reliably store data but become stuck at 0 or 1 or switch erratically between 0 and 1?
- ASoft error.
- BHard error.
- CHard failure.
- DSoft failure.
- EEpic failure.
47How is called a random, nondestructive event that alters the contents of one or more memory cells without damaging the memory?
- ASoft error.
- BHard error.
- CHard failure.
- DSoft failure.
- EEpic failure.
48Choose the feature(s) of first generation computer architecture
- AMagnetic core memory.
- BSemiconductor memory.
- CMachine code.
- DVacuum tubes.
- EAssembly language.
- FVacuum tubes, Assembly language.
49Choose the feature(s) of second generation computer architecture.
- AHigh level languages.
- BTransistors.
- C2 Kb memory, 10 KIPS.
- D2 Mb memory, 5 MIPS.
- EDifferent types of supported instructions.
- FHigh level languages, Transistors.
50Choose the feature(s) of third generation computer architecture
- AObject-Oriented programming.
- BFloating point arithmetic.
- CGraphics.
- DTimesharing.
- EUse of cache memory.
- FTimesharing, Use of cache memory.
51Choose the feature(s) of fourth generation computer architecture
- AObject-Oriented programming.
- BWide spread use of data communications.
- CSmallest in size.
- DUse of cache memory.
- EUse of drum memory or magnetic core memory.
- FObject-Oriented programming, Wide spread use of data communications, Smallest in size.
52How many generations of computer architecture are there?
- A4
- B3
- C2
- D1
- E5.
53Choose the years of the first generation computer architecture
- A1958-1964.
- B1964-1974
- C1974-present.
- D1945-1964.
- E1945-1958.
54Choose the years of the second generation computer architecture
- A1945-1958.
- B1964-1974.
- C1974-present.
- D1945-1964.
- E1958-1964.
55In 1976 Apple II computer model was released
- ATrue.
- BFalse.
56IBM System/360 Model 91 was introduced in 1966
- ATrue.
- BFalse.
57Choose two types of models for a computing machine
- AHarvard architecture, Von Neumann architecture.
- BOxford architecture, Stanford architecture.
58How many number systems are there?
- A1.
- B2.
- C3.
- D4.
59How a binary digit is called?
byte
digit
kilobyte
bit- Abyte.
- Bdigit.
- Ckilobyte.
- Dbit.
60 Four bits make octal digit
- ATrue.
- BFalse.
61Three bits make hexadecimal digit
- ATrue.
- BFalse.
62Octal and hexadecimal numbers are hard on use and conversion
- ATrue
- BFalse.
63 Which digits are used in octal number system?
- A0-7
- B0 and 1
- C0-9
- DAll digits.
64 What does CPI stand for?
- ACycles Per Instruction.
- BClocks Per Instruction.
- CCycles Per Interface.
- DClocks Per Interface.
65What is time elapsed to program execution?
- ACPU Time.
- BUser time + OS Time.
- CI/O waiting & Other programs.
- DCPU Time + I/O waiting & Other programs.
66The execution time of a program clearly depends on the number of instructions
- ATrue.
- BFalse
67 CPU Time = I * CPI / R. Which parameter requires special profiling software?
- ACycles Per instruction.
- BClock Rate.
- CNumbers of instructions.
- DExecution time.
68 Select the correct interpretation(s) of Amdahl's Law
- Ais used to compare computers' performance
- Bis used calculate the execution time of a program
- Cis used to find the maximum expected improvement
- Dit means that it is the algorithm that decides the speedup not the number of processors.
- Eis used to find the maximum expected improvement, it means that it is the algorithm that decides the speedup not the number of processors
69is used to find the maximum expected improvement
- A50%is used to compare computers' performance
- B0%is used calculate the execution time of a program
- Cis used to find the maximum expected improvement
- Dit means that it is the algorithm that decides the speedup not the number of processors
70 Into how many parts a program (or algorithm) which can be parallelized can be split up?
- A3
- B4
- C5.
- D2
71The time interval is called a clock rate
- Atrue
- Bfalse
72What does LRU stand for?
- ALeast Right Used
- BLast Recently User
- CLast Recently Used.
- DLeast Recently Used
73 How a memory unit accessed by contents is called?
Associative Memory- AAssociative Memory
- BContent Addressable Memory
- CAuxiliary Memory
- DCache Memory.
- EVirtual Memory
74Choose the access method(s)
- AParallel Access
- BIndirect Access
- CRandom Access
- DDirect Access
- ESequential Access
75 In which cache memory mapping technique any block from main memory can be placed anywhere in the cache?
- AAssociative Mapping
- BSet Associative Mapping
- CDirect Mapping
76 In LRU replacement algorithm, the block that is in the cache longest is replaced
- Atrue
- Bfalse
77In which cache memory mapping technique any memory block is mapped to exactly one block in the cache?
- ADirect Mapping
- BSet Associative Mapping
- CAssociative Mapping.
78In which cache memory mapping technique any memory block mapped to subset of cache locations?
- ASet Associative Mapping.
- BDirect Mapping
- CAssociative Mapping
79 Which type of memory accessed via the input/output channels?
- AMain Memory
- B%Cache Memory
- CVirtual Memory.
- DAuxiliary Memory
- ESecondary Memory
80Which type of memory stores frequently used data?
- Amain
- Bvirtual
- Cauixiluary
- Dsecondary
- Ecache
81 Choose the right formula for AMAT
- AAMAT = Hit time + Miss rate + Miss penalty
- BAMAT = Hit time * Miss rate + Miss penalty
- CAMAT = Hit time * Miss rate * Miss penalty.
- DAMAT = Hit time + Miss rate * Miss penalty
82 Choose the definition for compulsory misses
- AOccurs if the cache cannot contain all the blocks needed during execution of a program
- BOccurs if the block placement strategy is not fully associative
- CThe very first access to a block cannot be in the cache
83Choose the definition for capacity misses
- AOccurs if the cache cannot contain all the blocks needed during execution of a program
- BThe very first access to a block cannot be in the cache
- COccurs if the block placement strategy is not fully associative
84hoose the definition for conflict misses
- AOccurs if the block placement strategy is not fully associative
- BOccurs if the cache cannot contain all the blocks needed during execution of a program
- CThe very first access to a block cannot be in the cache
85 Select cache optimizations to reduce miss penalty
- Amultilevel Caches
- BGiving Reads Priority over Writes
- CWay Prediction
- DHigher associativity
86Select cache optimizations to increase the Cache Bandwidth
- ANonblocking Caches
- BMultibanked Caches
- CPipelined Cache Access
- DMultilevel Caches
- ESmall and Simple First-Level Caches
87In virtual memory, memory can be used efficiently because a section of program always loaded
- Atrue
- Bfalse
88 The advantage of virtual memory is that it takes less time to switch between applications because of additional memory
- Atrue
- Bfalse
89 Choose basic cache optimizations
- A\Compiler-Controlled Prefetching
- BNonblocking Caches
- Cmall and Simple First-Level Caches
- DMultilevel Caches
- EAvoiding Address Translation during Cache Indexing
90Choose advanced cache optimizations
- AGiving Reads Priority over Writes
- BLarger Cache Size
- CHardware Prefetching of Instructions and Data
- DMerging Write Buffer
- ECritical Word First and Early Restart
91Select cache optimizations to reduce hit time (both basic and advanced)
- AAvoiding Address Translation during Cache Indexing
- BSmall and Simple First-Level Caches
- CWay Prediction
- DCompiler Optimizations
- ECompiler-Controlled Prefetching
92 Physical address used by program, and which OS must translate into virtual address
- Atrue
- Bfalse
93 Process of instruction execution is divided into two or more steps, called
- Apipelining
- Bpipe stages
- Cpipe segments
- Dinstruction execution.
- Epipeline hazard
94Pipelining can only be implemented on hardware
- Atrue
- Bfalse
95 Choose hazard for the following definition: different instructions in different stages (or the same stage) conflicting for the same resource
- AStructural
- Bdata
- Ccontrol
96Choose hazard for the following definition: an instruction cannot continue because it needs a value that has not yet been generated by an earlier instruction
- AData
- BStructural
- CControl.
97Select the correct interpretation(s) of Amdahl's aw
- Ais used to compare computers' performance
- Bis used calculate the execution time of a program
- Cs used to find the maximum expected improvement
- Dit means that it is the algorithm that decides the speedup not the number of processors
Información
- Descripción
- Test sobre Untitled1, creado por aga aga el 26/03/2019.
- Autor
- aga aga
- Idioma
- English
- Visitas
- 8
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