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CZ3001 Advanced Computer Architecture
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- 1INTRODUCTION ALUPerform integer arithmetic operations and logical operations
- 2INTRODUCTION CONTROL UNITGenerate control signals for data movement and data storage operations, let ALU perform operations specified in the instruction
- 3INTRODUCTION CPUCentral Processing Unit
ALU + CU + Set of Registers - 4INTRODUCTION INSTRUCTION FETCHFetch instruction from memory and get ready to fetch the next instruction
- 5INTRODUCTION Instruction DecodeDecode instruction, fetch operands from register file
- 6INTRODUCTION ExecuteExecute ALU operation specified in the opcode of instruction
- 7INTRODUCTION MEMORY ACCESSPerform read/write for load/store operations
- 8INTRODUCTION WRITE BACKWrite the result back to register file
- 9PERFORMANCE METRICS AND ENCHANCEMENTExecution time = (number of instructions) x (number of cycles per instruction) x clock cycle time
Execution time = IC x CPI x Tc
IC: Instruction Count, CPI: Clock per instruction, Tc: Clock period - 10PERFORMANCE METRICS AND ENCHANCEMENT PERFORMANCE INDICATORExecution time is the indicator
Less execution time -> better performance = 1/execution time - 11INTRODUCTION REGISTERSStore the input to be used by ALU and
control unit, and sometimes the computed
results. - 12PERFORMANCE METRICS AND ENCHANEMENT AVERAGE CPIAVERAGE CPI = (total no. of cycles)/total no. of instructions in program (IC)
No. of cycles = SUM(IC k x CPI k), for some category k
Execution Time = IC X Average CPI X Tc - 13PERFORMANCE METRICS AND ENHANCEMENT FACTORS AFFECTING EXECUTION TIME1. Clock Period: datapath design and implementation, semiconductor technology
2. Instruction Count: isa, application/program
3. Clocks Per Instrutions: isa, datapath, pipelined and parallel HW - 14PERFORMANCE METRICS AND ENHANCEMENT CPI AND DATAPATHMulti Cycle Datapath (CPI > 1) < Instruction pipelining (CPI = 1) < Instruction level parallel processing < VLIW/Superscalar (CPI < 1)
- 15PERFORMANCE METRICS AND ENHANCEMENT SPEEDUPSpeed up of computer B over A or computer B is the enhanced version of A:
Speed Up = time execution for A / time execution for B - 16PERFORMANCE METRICS AND ENHANCEMENT ENHANCED VS UNENHANCED1. Fraction E is enhanced by factor of S,
U = (1 - E) ⇒ U is not enhanced fraction
Time for unenhanced fraction = T x U
Time for enhanced fraction = T x E / S
Total exection time for enhanced machine T' = T x (1 - E) + T x E / S
2. Speedup = T/T'
3.Maximum speedup = T/(T X U) = 1/U, when S is very large, T' = T x U - 17PERFORMANCE METRICS AND ENHANCEMENT AMDAHL'S LAWSpeedup via parallelism is limited by componen of application that cannot be enhanced ⇒ speed up limited by factor of 1/U
- 18PERFORMANCE METRICS AND ENHANCEMENT THROUGHPUT RATENumber of output produced in one clock cycle.
Increased by parallel processing and/or pipelined processing - 19PERFORMANCE METRIC AND ENHANCEMENT RESPONSE TIME/LATENCYInterval between time when system receive first input and gives first output: (measured in clock cycles)
Time interval between stimulation and response
Important for Hard-Real Time system - 20PERFORMANCE METRIC AND ENHANCEMENT MIPS (MILLION INSTRUCTIONS PER SECONDS)1. Native MIPS = IC/(Execution Time X 10^6)
2. Peak MIPS = choose sequence that provide maximum MIPS
3. Relative MIPS = execution time ref x MIPS ref / (execution time machine being evaluated)
4. Varies with ISA (complexity), and choice of instruction mix
5. Does not guarantee better performance
6. Relative MIPS helps rate evolving design of same computer - 21PERFORMANCE METRIC AND ENHANCEMENT FLOPS (FLOATING-POINT OPERATIONS PER SECONDS)FLOPS = number of floating-point operations / (execution time x 10^6)
- 22PERFORMANCE METRIC AND ENHANCEMENT PERFORMANCE AVERAGINGCompare the speedup and execution time
1. Use of AM: arithmetic mean
average execution time = (1/n) x sum (T k x W k )
n: number of programs, k: 1, 2, .. n, w: multiple of times
2. Use of GM: geometric mean, when ratio is given
average speedup = square_root(product(s k));
s: speedup, k: 1, 2, .., n
3. Use of HM: harmony mean when MIPS is given
average MIPS = n / (sum(1/m k))
n: number of programs, k: 1, 2, .., n,
m: MIPS - 23CONCEPT OF PARALLEL PROCESSING AND PIPELININGTotal Time = Total computation time + total communication time
1. Time for distribution = d x k,
2. Time for computation of local sum
3. Time for collection of partial results = d x k
4. Time to add partial results = t x k
Total Time = 1 + 2 + 3 + 4
5. Total computation time = total computation of local sum + time for partial results
6. Total distribution time = time for distribution + time for collection
k: number of elements - 24CONCURRENT COMPUTING: PARALLEL PROCESSING AND PIPELINING PIPELINING (CONCURRENCY)very fast
only useful for large number of similar tasks
latency increases with number of pipeline stages - 25PARALLEL PROCESSING AND PIPELINING PARALLELISMINSTRUTION LEVEL PARALELLISM: multiple instructions executed concurrently
DATA PARALELLISM: each processor perform same task on different data
TASK PARALLELISM: processor performs different independenttask - 26PARALLEL PROCESSING AND PIPELINING CLOCKClock signal: periodic pulse
Working processors is governed (synchronized) by clock
Data movement is governed by clock - 27PARALLEL PROCESSING AND PIPELINING CRITICAL PATHmaximum of all computation time (propagation time) required by any adjacent register (input-output)
duration of clock period need to be more or equal to critical path - 28POWER DISSIPATION DYNAMIC POWERmainly due to charging and
discharging of pseudo capacitors– when a logic state changes from 0 → 1 or
from 1 → 0
short-circuit power (due to the current from Vdd to GND when both transistors are ON for a short time) - 29POWER DISSIPATION STATIC POWERconsumed anytime the processor is powered on.
mainly due to leakage current - 30POWER DISSIPATION DYNAMIC POWER BEHAVIOURPdyn = A C V² f
C: total load capacitance in the circuit, increase with logic circuits used
f: clock frequency
V : operating voltage (also called Vdd)
A: switching activity factor: the fraction of transistors switch during a clock
cycle (in average). - 31POWER DISSIPATION STATIC POWER BEHAVIOURStatic Power = V x I leak
where Ileak is leakage current and V is
operating voltage - 32ISA MEMORY ORGANISATIONByte addressable: each memory address references to one byte, memory address is the index of the memory array
- 33ISA WORDFixed-sized group of bits handled as one unit by the processor.
How many words can be addressed?
2^(word-length) / #bytes in group
- Address of each instruction is multiple of #bytes in group
- Address of next instruction is current address + #bytes of word
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- Undergraduate Computer Science Fichas sobre CZ3001 Advanced Computer Architecture, creado por Deka Auliya el 23/04/2015.
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- Deka Auliya
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