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Description
Flashcards by Malachy Moran-Tun, updated more than 1 year ago
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Created by Malachy Moran-Tun
about 3 years ago
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| Question | Answer |
| What is the Purpose of the Control Unit? | > Overall control of the CPU - Activates and communicates with all parts of the CPU (as well as other components of the computer) > Mainly executes program instructions via the F.D.E. cycle > Controls the flow of data inside and outside the CPU - Responsible for read and write requests to memory |
| What is the Purpose of the Program Counter? | > Holds the memory address of the next instruction to be fetched from RAM - Either incremented or changed via the CIR (if the code branches, in which case the previous value is added to a stack) > Works closely with the MAR - At the start of every cycle, the address in the PC is copied to the MAR |
| What is the Purpose of the Memory Address Register? | > Holds the address of the memory location from which data is to be read / written > Sends the address to memory down the Address Bus |
| What is the Purpose of the Memory Data Register? | > Holds the actual data received from RAM (or was written to RAM) > This data is sent from RAM down the Data Bus |
| What is the Purpose of the Current Instruction Register? | > Holds the instruction currently being executed > Contains the opcode and operand(s) of the current instruction - Opcode - the operation to be done to the data - Operand - the data affected by the operation |
| What is the Purpose of the Arithmetic Logic Unit? | > Performs arithmetic and logical operations of data - Includes addition, subtraction, multiplication, division, as well as bitwise shifts and logical operations (e.g., AND, OR, NOT etc.) |
| What is the Purpose of the Accumulator? | > Temporary register that stores the immediate results of calculations from the ALU |
| What is the Purpose of the Address Bus? | > Carries memory addresses from the MAR that identify where the data is being read from and written to |
| What is the Purpose of the Data Bus? | > Carries the binary data that makes up information (data and instructions) being transmitted to the MDR |
| What is the Purpose of the Control Bus? | > Carries command and control signals to and from every other component of the CPU, to ensure that everything stays synchronised |
| Generally, what is a Bus? | > A vehicle that is always dirty or > A group of parallel wires that connect CPU components in order to pass signals between them |
| What is a Bus Request and a Bus Grant? | > Request - indicates a device is requesting the use of the Data Bus > Grant - indicates the CPU has granted access to the Data Bus |
| What is Clock Speed and How does it affect CPU Performance? | > The number of cycles that a single processor core can carry out per second (measured in Hertz, Hz) > A faster clock speed means that more instructions are fetched, decoded, and executed in a second |
| What is the Cache and How does it affect CPU Performance? | > Temporary storage that is extremely fast for the CPU - slower than registers but much faster than requests to / from RAM - It does not require instructions to be fetched via slow buses > Stores frequently used data - the CPU checks the cache first, then the RAM > Too much cache can be detrimental, as there's more data to search through every time data is required > L1 - on the CPU chip, smallest and fastest, most expensive (also known as primary or internal cache) > L2 - on the motherboard or CPU, larger but slower > L3 - on the motherboard, larger again, but slowest |
| What are Cores and How do they affect CPU Performance? | > Each core can process data independently from the rest, allowing for simultaneous processing > It allows for parallel processing and multitasking > Software must be designed to use multiple cores, otherwise there is no performance benefit |
| What is a GPU and How does it affect Performance? | > Graphics processing unit > Contains specialised circuits for handling graphics and image processing > Relieves the processing load on the CPU, freeing it to do other things > Using high-end cards can vastly speed up software that renders graphics, i.e., 3D Design software (CAD) and games |
| What is Pipelining and How does it affect CPU Performance? | > Each core performs one part of the fetch, decode, execute cycle for each instruction, which speeds up performance as it doesn't have to switch operations > Branching can cause issues with pipelining since it may end up processing an instruction that will be skipped after an if statement |
| What is Word Size and How does it affect Performance? | > Number of bits a CPU can process in one cycle (i.e., 8-bit, 16-bit, 32-bit, 64-bit) > Modern systems have 64-bit architectures, although sometimes have backwards-compatibility |
| What are the Two Types of Parallel Processing and their Differences? | > SIMD - Single Instruction, Multiple Data > Same program can be executed on different data sets at the same time > One Control Unit handles multiple ALUs > MIMD - Multiple Instruction, Multiple Data > Different programs can be executed on different processors at the same time > Multiple Control Units each handle their own ALUs |
| What is Distributed Computing? | > Alternative to Parallel Processing > Uses the Internet to process a large problem > Each node takes on a small part of the problem > Each node has their own memory, unlike Parallel Processing, where it is shared |
| What is the Von Neumann Architecture? | > Single shared memory and shared bus for data and instructions > Bus transfers either data or instructions > Bottleneck as the instruction cannot be completed until both data and instructions have been fetched and decoded |
| What is the Harvard Architecture? | > Two separate memory and data buses for data and instructions > Each memory has a dedicated bus which allows it to fetch data and instructions simultaneously > Expensive and complex to implement |
| What is the Contemporary Architecture? | > Uses aspects of both Von Neumann and Harvard > Von Neumann architecture is used for the main memory - contains a bottleneck > Harvard is used for the cache - data and instructions are fetched independently - no bottleneck |
| What is CISC Architecture? | > Complex Instruction Set Computing > Aims to complete the task in as few lines of assembly as possible > Processor hardware and circuitry has to be more complicated > Complex instructions that resembles high-level language > Compiler has to do little work to translate the high-level language to assembly > Instructions may take more than one cycle - no pipelining > Used in PCs - x86 processors |
| What is RISC Architecture? | > Uses simple instructions that are executed within a single clock cycle > Instructions separated into smaller commands > More lines of code required - compiler has to do more conversion work & more RAM is required to store instructions > Processing takes up less energy; each instruction can be completed in a single clock cycle, and pipelining can be applied > Requires fewer transistors and less complex hardware, leaving more room for general purpose registers, cache, and therefore lower energy requirements > Used in smartphones, tablets, and embedded system via ARM processors |
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