Fetch Execute Cycle

Jay Patel
Mind Map by Jay Patel, updated more than 1 year ago
Jay Patel
Created by Jay Patel about 5 years ago
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Description

The Fetch Execute Cycle as described for AQA AS Computing
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Resource summary

Fetch Execute Cycle
1 MAR <-- [PC]
1.1 The contents of the Program Counter are copied into the Memory Address Register
1.1.1 This is so that the next instruction can be fetched
2 MBR<--[Memory] PC <-- [PC]+1
2.1 These two actions happen simultaneously
2.1.1 The contents of the Memory Address specified in the MAR are fetched (copied) from memory and placed in the Memory Buffer Register
2.1.2 The contents of the Program Counter are incremented so that it now points to the address of the NEXT instruction
3 CIR <--[MBR]
3.1 The contents of the Memory Buffer Register are copied to the Current Instruction Register
4 [CIR] Decode
4.1 Execute
4.1.1 The OPCODE may require data to be fetched from Memory into the Accumulator
4.1.2 The OPCODE may require data to be put into the Accumulator from the OPERAND
4.1.3 The OPCODE may require an operation to be applied to the contents of the Accumulator
4.2 The contents of the Current Instruction Register are now decoded by examining the OPCODE
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