Copy and Edit

Vhdl source file

Description

CSD project_1 (EX1A)
Cristina Pérez9355
Mind Map by Cristina Pérez9355, updated more than 1 year ago
Cristina Pérez9355
Created by Cristina Pérez9355 almost 9 years ago
35
0
0

Resource summary

Vhdl source file
  1. synthesis
    1. circuit synthesized for a target chip PDL, FPGA
      1. VHDL-based simulation TestBench
        1. behavioral high-level simulation
          2. Gate-level simulation
            1. Run simulation
          3. LAB test & measurements
        2. Circuit_1.vhd
          1. writing a text file scriptum editor
            1. equation
            2. schematic entry translation
              1. schematic
              Show full summary Hide full summary

              Want to create your own Mind Maps for free with GoConqr? Learn more.

              Similar

              Descripción de hardware en VHDL
              BENIGNO MUÑOZ
              MINISTERIO DE CULTURA
              Raúl Espiña
              Pensamiento Lógico Computacional
              Bosco Cortés
              EXAMEN 3
              wilson ac
              VHDL
              Fabian Fonseca Edgar
              Of Mice & Men Themes - Key essay points
              Lilac Potato
              Biology B2.1
              Jade Allatt
              New GCSE Maths
              Sarah Egan
              GCSE - Introduction to Economics
              James Dodd
              PSBD TEST 1
              amrik.sachdeva
              What are they doing?
              Tamara Urzhumova
              Browse Library