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Vhdl source file

Description

CSD project_1 (EX1A)
Cristina Pérez9355
Mind Map by Cristina Pérez9355, updated more than 1 year ago
Cristina Pérez9355
Created by Cristina Pérez9355 over 6 years ago
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Resource summary

Vhdl source file
  1. synthesis
    1. circuit synthesized for a target chip PDL, FPGA
      1. VHDL-based simulation TestBench
        1. behavioral high-level simulation
          1. Gate-level simulation
            1. Run simulation
          2. LAB test & measurements
        2. Circuit_1.vhd
          1. writing a text file scriptum editor
            1. equation
            2. schematic entry translation
              1. schematic
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