Loading [MathJax]/jax/output/HTML-CSS/fonts/TeX/fontdata.js

We have detected that Javascript is not enabled in your browser. The dynamic nature of our site means that Javascript must be enabled to function properly. Please read our terms and conditions for more information.

Next up

Descripción de hardware en VHDL

BENIGNO MUÑOZ

Copy and Edit

Vhdl source file

Description

CSD project_1 (EX1A)

Mind Map by Cristina Pérez9355, updated more than 1 year ago

	Created by Cristina Pérez9355 over 9 years ago

(0)

Resource summary

Vhdl source file

synthesis
1. circuit synthesized for a target chip PDL, FPGA
  1. VHDL-based simulation TestBench
    1. behavioral high-level simulation
    2. Gate-level simulation
      1. Run simulation
  2. LAB test & measurements
Circuit_1.vhd
writing a text file scriptum editor
1. equation
schematic entry translation
1. schematic

Show full summary Hide full summary

0 comments

There are no comments, be the first and leave one below:

To join the discussion, please sign up for a new account or log in with your existing account.

Want to create your own Mind Maps for free with GoConqr? Learn more.

Similar

MINISTERIO DE CULTURA

Raúl Espiña

Pensamiento Lógico Computacional

Bosco Cortés

EXAMEN 3

wilson ac

VHDL

Fabian Fonseca Edgar

CPA Exam Topics and breakdown

joemontin

GCSE History – Social Impact of the Nazi State in 1945

Ben C

Language Techniques

Anna Wolski

Disney's 12 Principles of Animation

Emiloly Bringabrolly

A Christmas Carol (Key Quotes)

Samira Choudhury

Métodos y reglas de interpretación jurídica Constitucional y Ordinaria

jose calle

Browse Library