Truth table and inputs/outputs

Description

CSD project_1 (EX1A)
cristinaaa.perez
Mind Map by cristinaaa.perez, updated more than 1 year ago More Less
Cristina Pérez9355
Created by Cristina Pérez9355 almost 9 years ago
cristinaaa.perez
Copied by cristinaaa.perez almost 9 years ago
4
0

Resource summary

Truth table and inputs/outputs
  1. Use decoder4to16 (form by two chip74LS138)
    1. Transform into a vhdl file with 4 inputs, 16 outputs and 3 Enables
      1. Adequate to our parameters
        1. ispLEVER, to compile all together
          1. ActiveHDL to simulate the results
            1. Adequate to our circuit_1
              1. Repeat the process
            2. Synplify to discover our new circuit designed
      Show full summary Hide full summary

      Similar

      Descripción de hardware en VHDL
      BENIGNO MUÑOZ
      MINISTERIO DE CULTURA
      Raúl Espiña
      Pensamiento Lógico Computacional
      Bosco Cortés
      EXAMEN 3
      wilson ac
      Rates of Reaction
      Evie Papanicola
      French Grammar- Irregular Verbs
      thornamelia
      The Many Conjugations of Spanish! Wow!
      hannahkathryn5
      Conferences of the Cold War
      Alina A
      Language Techniques
      Anna Wolski
      Cloud Data Integration Specialist Certification
      James McLean