3.3.3: Computer architectures

Adam Cook
Mind Map by Adam Cook, updated more than 1 year ago
Adam Cook
Created by Adam Cook over 5 years ago


Mind map for A2 Computing Master Mind Map *FINISHED*

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3.3.3: Computer architectures
  1. Von Neumann
    1. Takes each instruction serially
      1. Performs each instruction before carrying out the next.
        1. Instructions and data stored together in memory
        2. FETCH
            1. 1: PC holds address of next instruction to be executed
              1. 2: Address is copied to the MAR
                1. 3: Data in address at MAR is copied to MDR
                  1. 4: Contents of MDR copied to CIR
                    1. 5: Contents of PC are incremented
                    2. DECODE
                        1. 6: Contents of CIR divided into code for operation to be carried out and the address that the data will be used by
                          1. 7: Control Unit interprets the code so that the processor knows what to do next.
                          2. EXECUTE
                              1. 8: Address is copied from the CIR to the MAR
                                1. 9: Data found in the MAR is copied to the MDR
                                  1. 10: Data is used
                                  2. Types of processor
                                    1. Co-processor
                                        1. Additonal processor for a specific task (such as a GPU)
                                          1. Most co-processors do not fetch instructions for themselves
                                          2. Parallel Processor
                                            1. With Fetch - Decode - Execute cycle
                                                1. A processor for each step of the Fetch - Decode - Execute cycle
                                                  1. Speeds up process as next instruction can be fetched before current instruction has finished processing.
                                                  2. With Pipelining
                                                      1. One main processor that splits jobs up into tasks and farms each tasks to other processors
                                                        1. Main Processor Fetches and Decodes task and splits execution into individual tasks and sends to other processors to execute.
                                                      2. Array processor
                                                          1. Multiple processors compute mathematics on arrays of numbers simultaneously.
                                                            1. Numbers are all fetched and then executed simultaneously.
                                                            2. Advantages and Disadvantages of Alternative Processors
                                                              1. Advantages
                                                                1. Faster Processing
                                                                  1. More than one instruction can be executed at the same time
                                                                    1. Different processors can handle different parts of the same job.
                                                                    2. Disadvantages
                                                                      1. Requires processors to be synced together
                                                                        1. Program has to be written to use multiple processors
                                                                          1. Programs are more complex to write, test and debug.
                                                                      2. CISC vs RISC
                                                                        1. CISC
                                                                          1. Every computer operation has an instruction
                                                                            1. Each operation has a binary code (Op-Code) associated with it
                                                                              1. Complex Instruction Set
                                                                                1. More bits needed to represent each instruction
                                                                                2. RISC
                                                                                  1. Reduced Instruction Set
                                                                                    1. Typically used in handheld devices
                                                                                    2. Recognises fewer instructions
                                                                                      1. Less bits needed to represent instructions
                                                                                        1. Missing instructions made up with programming techniques
                                                                                          1. Less complex circuitry
                                                                                            1. Op-code and address allocated same number of bits
                                                                                              1. Registers are all the same size
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