Quiz
CSA IITU PART 2 (235)
Perguntas do quiz (106)
1109. What is a “Kernel” in Cache Memory?
- Ao Execution in the OS that is neither idle nor in synchronization access
- Bo Execution or waiting for synchronization variables
- Co Execution in user code
2108. What is a “Synchronization” in Cache Memory?
- Ao Execution in the OS that is neither idle nor in synchronization access
- Bo Execution in user code
- Co Execution or waiting for synchronization variables
3107. How many main levels of Cache Memory?
- A3
- B2
- C6
- D8
4106. How many size of Cache L3 is true approximately? :
- Ao 3 MB
- Bo 256 KB
- Co 256 MB
5105. How many size of Cache L2 is true approximately? :
- Ao 256 KB
- Bo 4 KB
- Co 32 MB
6104. How many size of Cache L1 is true approximately? :
- Ao 8 KB
- Bo 256 KB
- Co 2 MB
7103. Little’s Law and a series of definitions lead to several useful equations for
- Ao Average length of queue
- Bo Average number of tasks in service
8102. Little’s Law and a series of definitions lead to several useful equations for “Length server” - :
- Ao Average number of tasks in service
- Bo Average length of queue
9101. Little’s Law and a series of definitions lead to several useful equations for “Time system” - :
- Ao Average time/task in the system, or the response time, which is the sum of Time queue and Time server
- Bo Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
- Co Average time per task in the queue
10100. Little’s Law and a series of definitions lead to several useful equations for “Time queue” - :
- Ao Average time per task in the queue
- Bo Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
- Co Average time/task in the system, or the response time, which is the sum of Time queue and Time server
1199. Little’s Law and a series of definitions lead to several useful equations for “Time server” - :
- Ao Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
- Bo Average time per task in the queue
- Co Average time/task in the system, or the response time, which is the sum of Time queue and Time server
1298. If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time” - ?:
- Ao The time from the reception of the response until the user begins to enter the next command
- Bo The time for the user to enter the command
- Co The time between when the user enters the command and the complete response is displayed
1397. If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time” - ?:
- Ao The time between when the user enters the command and the complete response is displayed
- Bo The time for the user to enter the commando The time for the user to enter the command
- Co The time from the reception of the response until the user begins to enter the next command
1496. If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Entry time” - ? :
- Ao The time for the user to enter the command
- Bo The time between when the user enters the command and the complete response is displayed
- Co The time from the reception of the response until the user begins to enter the next command
1595. At storage systems Gray and Siewiorek classify faults what does mean “Environmental faults”? :
- Ao Fire, flood, earthquake, power failure, and sabotage
- Bo Faults in software (usually) and hardware design (occasionally)
- Co Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
1694. At storage systems Gray and Siewiorek classify faults what does mean “Operation faults”? :
- Ao Mistakes by operations and maintenance personnel
- Bo Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
- Co Faults in software (usually) and hardware design (occasionally)
1793. At storage systems Gray and Siewiorek classify faults what does mean “Design faults”? :
- Ao Faults in software (usually) and hardware design (occasionally)
- Bo Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
- Co Mistakes by operations and maintenance personnel
1892. At storage systems Gray and Siewiorek classify faults what does mean “Hardware faults”? :
- Ao Faults in software (usually) and hardware design (occasionally)
- Bo Mistakes by operations and maintenance personnel
- Co Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
1991. What is a RAID 4?
- Ao Many applications are dominated by small accesses
- Bo Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed
- Co Also called mirroring or shadowing, there are two copies of every piece of data
2090. What is a RAID 3?
- Ao Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed
- Bo Many applications are dominated by small accesses
- Co Also called mirroring or shadowing, there are two copies of every piece of data
2189. What is a RAID 2?
- Ao This organization was inspired by applying memory-style error correcting codes to disks
- Bo It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
- Co Also called mirroring or shadowing, there are two copies of every piece of data
2288. What is a RAID 1?
- Ao Also called mirroring or shadowing, there are two copies of every piece of data
- Bo It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
- Co This organization was inspired by applying memory-style error correcting codes to disks
2387. What is a RAID 0?
- Ao It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
- Bo Also called mirroring or shadowing, there are two copies of every piece of data
- Co This organization was inspired by applying memory-style error correcting codes to disks
2486. A virus classification by target includes the following categories, What is a File infector?
- Ao Infects files that the operating system or shell consider to be executable
- Bo A typical approach is as follows
- Co The key is stored with the virus
- Do Far more sophisticated techniques are possible
2585. In Non-Blocking Caches what does mean “Early restart”?
- Ao Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
- Bo Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
2684. In Non-Blocking Caches what does mean “Critical Word First”?
- Ao Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
- Bo Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
2783. Storage Systems, “Higher associativity to reduce miss rate” -
- Ao Obviously, increasing associativity reduces conflict misses
- Bo The obvious way to reduce capacity misses is to increase cache capacity
- Co The simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size
2882. Storage Systems, “Bigger caches to reduce miss rate” -
- Ao The obvious way to reduce capacity misses is to increase cache capacity
- Bo Obviously, increasing associativity reduces conflict misses
- Co The simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size
2981. Storage Systems, “Larger block size to reduce miss rate” -
- Ao The simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size
- Bo The obvious way to reduce capacity misses is to increase cache capacity
- Co Obviously, increasing associativity reduces conflict misses
3080. At Critical Word First for Miss Penalty chose correct sequence of Blocking Cache with Critical Word first “Order of fill”:
- Ao 3,4,5,6,7,0,1,2
- Bo 0,1,2,3,4,5,6,7
3179. At Critical Word First for Miss Penalty chose correct sequence of Basic Blocking Cache “Order of fill”:
- Ao 0,1,2,3,4,5,6,7
- Bo 3,4,5,6,7,0,1,2
3278. What does MAF?
- Ao Miss Address File
- Bo Map Address File
- Co Memory Address File
3377. What does mean MSHR?
- Ao Miss Status Handling Register
- Bo Map Status Handling Reload
- Co Mips Status Hardware Register
- Do Memory Status Handling Register
3476. Non-Blocking Cache Timeline for “Miss Under Miss” the sequence is -?
- Ao CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->Miss Penalty->CPU time
- Bo CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
- Co CPU time-Cache Miss-Miss Penalty-CPU time
3575. Non-Blocking Cache Timeline for “Hit Under Miss” the sequence is -?
- Ao CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
- Bo CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time
- Co CPU time-Cache Miss-Miss Penalty-CPU time
3674. Non-Blocking Cache Timeline for “Blocking Cache” the sequence is - ?
- Ao CPU time-Cache Miss-Miss Penalty-CPU time
- Bo CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
- Co CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time
3773. In Multilevel Caches “Misses per instruction” equals =
- Ao misses in cache / number of instructions
- Bo misses in cache / accesses to cache
- Co misses in cache / CPU memory accesses
3872. In Multilevel Caches “Global miss rate” equals =
- Ao misses in cache / CPU memory accesses
- Bo misses in cache / accesses to cache
- Co misses in cache / number of instructions
3971. In Multilevel Caches “Local miss rate” equals =
- Ao misses in cache / accesses to cache
- Bo misses in cache / number of instructions
- Co misses in cache / CPU memory accesses
4070. What is a Conflict?
- Ao misses that occur because of collisions due to less than full associativity
- Bo first-reference to a block, occur even with infinite cache
- Co cache is too small to hold all data needed by program, occur even under perfect replacement policy
4167. At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches:
- Ao Allow one instruction to branch multiple directions
- Bo Speculative operations that don’t cause exceptions
4266. What is an ALAT? :
- Ao Advanced Load Address Table
- Bo Allocated Link Address Table
- Co Allowing List Address Table
- Do Addition Long Accessibility Table
4365. h Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
- Ao Hardware to check pointer hazards
- Bo Speculative operations that don’t cause exceptions
4464. At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion?
- Ao Speculative operations that don’t cause exceptions
- Bo Hardware to check pointer hazards
4563. At VLIW by “performance and loop iteration” which time is shorter?
- Ao Software Pipelined
- Bo Loop Unrolled
4662. At VLIW by “performance and loop iteration” which time is longer?
- Ao Loop Unrolled
- Bo Software Pipelined
4761. What is “VLIW”?
- Ao Very Long Instruction Word
- Bo Very Light Internal Word
- Co Very Less Interpreter Word
- Do Very Low Invalid Word
4860. Out-of-Order Control Complexity MIPS R10000 which element is not in Control Logic?
- Ao Integer Datapath
- Bo CLK
- Co Free List
- Do Address Queue
4959. Out-of-Order Control Complexity MIPS R10000 which element is in Control Logic?
- Ao Register name
- Bo Instruction cache
- Co Data tags
- Do Data cache
5058. At VLIW “Superscalar Control Logic Scaling” which parameters are used?
- Ao Width and Lifetime
- Bo Width and Height
- Co Time and Cycle
- Do Length and Addition
5157. What is an IQ?
- Ao Issue Queue
- Bo Internal Queue
- Co Interrupt Queue
- Do Instruction Queue
5256. What is a FL?
- Ao Free List
- Bo Free Last
- Co Free Launch
- Do Free Leg
5355. What is a RT?
- Ao Rename Table
- Bo Recall Table
- Co Relocate Table
- Do Remove Table
5454. Speculating on Exceptions “Recovery mechanism” is -
- Ao Only write architectural state at commit point, so can throw away partially executed instructions after exception
- Bo Exceptions are rare, so simply predicting no exceptions is very accurate
- Co An entity capable of accessing objects
- Do None of them
551. Speculating on Exceptions “Check prediction mechanism” is -
- Ao Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
- Bo Exceptions are rare, so simply predicting no exceptions is very accurate
- Co The way in which an object is accessed by a subject
- Do None of them
5652. Speculating on Exceptions “Prediction mechanism” is -
- Ao Exceptions are rare, so simply predicting no exceptions is very accurate
- Bo Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
- Co Only write architectural state at commit point, so can throw away partially executed instructions after exception
- Do None of them
5751. What is about Superscalar means “F-D-X-M-W”?
- Ao Fetch, Decode, Execute, Memory, Writeback
- Bo Fetch, Decode, Instruct, Map, Write
- Co Fetch, Decode, Excite, Memory, Write
- Do Fetch, Decode, Except, Map, Writeback
5850. How many stages used in Superscalar (Pipeline)?
- A5
- B4
- C6
- D7
5949. What is a SB?
- Ao Scoreboard
- Bo Scorebased
- Co Scalebit
- Do Scaleboard
6048. What is a PRF?
- Ao Physical Register File
- Bo Pending Register File
- Co Pipeline Register File
- Do Pure Register File
6147. What is a FSB?
- Ao Finished Store Buffer
- Bo Finished Stack Buffer
- Co Finished Stall Buffer
- Do Finished Star Buffer
6246. What is a ROB?
- Ao Reorder Buffer
- Bo Read Only Buffer
- Co Reload Buffer
- Do Recall Buffer
6345. What is a ARF:
- Ao Architectural Register File
- Bo Architecture Relocation File
- Co Architecture Reload File
- Do Architectural Read File
6444. Which of the following formula is true about Issue Queue for “Instruction Ready”:
- Ao Instruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no structural hazards
- Bo Instruction Ready = (!Vsrc0 || !Psrc1)&&(!Vsrc1 || !Psrc0)&& no structural hazards
- Co Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc1)&& no structural hazards
- Do Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc0)&& no structural hazards
6543. How many instructions used in Distributed Superscalar 2 and Exceptions?
- A4
- B3
- C2
- D1
6642. How many issue queue used in Distributed Superscalar 2 and Exceptions:
- A4
- B3
- C2
- D1
6741. How many issue queue used in Centralized Superscalar 2 and Exceptions?
- A4
- B3
- C2
- D1
6840. Little’s Law and a series of definitions lead to several useful equations for “Length queue” -:
- Ao Average length of queue
- Bo Average number of tasks in service
6939. Little’s Law and a series of definitions lead to several useful equations for “Length server” - :
- Ao Average number of tasks in service
- Bo Average length of queue
7038. Little’s Law and a series of definitions lead to several useful equations for “Time system” - :
- Ao Average time/task in the system, or the response time, which is the sum of Time queue and Time server
- Bo Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
- Co Average time per task in the queue
7137. Little’s Law and a series of definitions lead to several useful equations for “Time queue” - :
- Ao Average time per task in the queue
- Bo Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
- Co Average time/task in the system, or the response time, which is the sum of Time queue and Time server
7236. Little’s Law and a series of definitions lead to several useful equations for “Time server” - :
- Ao Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
- Bo Average time per task in the queue
- Co Average time/task in the system, or the response time, which is the sum of Time queue and Time server
7335. If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time” - ?:
- Ao The time from the reception of the response until the user begins to enter the next command
- Bo The time for the user to enter the command
- Co The time between when the user enters the command and the complete response is displayed
7434. If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time” - ?:
- Ao The time between when the user enters the command and the complete response is displayed
- Bo The time for the user to enter the command
- Co The time from the reception of the response until the user begins to enter the next command
7533. What is kernel process?
- Ao Provide at least two modes, indicating whether the running process is a user process or an operating system process
- Bo Provide at least five modes, indicating whether the running process is a user process or an operating system process
- Co Provide a portion of the processor state that a user process can use but not write
- Do None of them
7632. What does DDR stands for?
- Ao Double data rate
- Bo Dual data rate
- Co Double data reaction
- Do None of them
7731. What does DRAM stands for?
- Ao Dynamic Random Access memory
- Bo Dual Random Access memory
- Co Dataram Random Access memory
7830. What does SRAM stands for?
- Ao Static Random Access memory
- Bo System Random Access memory
- Co Short Random Accessmemory
- Do None of them
7929. What is the cycle time?
- Ao The minimum time between requests to memory.
- Bo Time between when a read is requested and when the desired word arrives
- Co The maximum time between requests to memory.
- Do None of them
8028. What is the access time?
- Ao Time between when a read is requested and when the desired word arrives
- Bo The minimum time between requests to memory.
- Co Describes the technology inside the memory chips and those innovative, internal organizations
- Do None of them
8127. Data Hazard:
- Ao An instruction depends on a data value produced by an earlier instruction
- Bo An instruction in the pipeline needs a resource being used by another instruction in the pipeline
- Co Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
8226. Structural Hazard:
- Ao An instruction in the pipeline needs a resource being used by another instruction in the pipeline
- Bo An instruction depends on a data value produced by an earlier instruction
- Co Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
8325. Exploit spatial locality:
- Ao by fetching blocks of data around recently accessed locations
- Bo by remembering the contents of recently accessed locations
- Co None of them
8424. Exploit temporal locality:
- Ao by remembering the contents of recently accessed locations
- Bo None of them
- Co by fetching blocks of data around recently accessed locations
8523. Reduce Miss Rate: High Associativity. Empirical Rule of Thumb:
- Ao Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
- Bo If cache size is doubled, miss rate usually drops by about √2
- Co None of them
8622. Reduce Miss Rate: Large Cache Size. Empirical Rule of Thumb:
- Ao If cache size is doubled, miss rate usually drops by about √2
- Bo Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
- Co None of them
8721. Cache Hit -
- Ao Write Through – write both cache and memory, generally higher traffic but simpler to design
- Bo write cache only, memory is written when evicted, dirty bit per block avoids unnecessary write backs, more complicated
- Co No Write Allocate – only write to main memory
8820. Least Recently Used (LRU):
- Ao cache state must be updated on every access
- Bo Used in highly associative caches
- Co FIFO with exception for most recently used block(s)
8919. What is Computer Architecture?
- Ao is the design of the abstraction/implementation layers that allow us to execute information processing applications efficiently using manufacturing technologies
- Bo is a group of computer systems and other computing hardware devices that are linked together through communication channels to facilitate communication and resource-sharing among a wide range of users
- Co the programs used to direct the operation of a computer, as well as documentation giving instructions on how to use them
9018. What is a Bandwidth-Delay Product:
- Ao is amount of data that can be in flight at the same time (Little’s Law)
- Bo is time for a single access – Main memory latency is usually >> than processor cycle time
- Co is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
9117. What is a Bandwidth:
- Ao a is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
- Bo is time for a single access – Main memory latency is usually >> than processor cycle time
- Co is amount of data that can be in flight at the same time (Little’s Law)
9216. Control Hazard:
- Ao Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
- Bo An instruction depends on a data value produced by an earlier instruction
- Co An instruction in the pipeline needs a resource being used by another instruction in the pipeline
9315. Data Hazard:
- Ao An instruction depends on a data value produced by an earlier instruction
- Bo An instruction in the pipeline needs a resource being used by another instruction in the pipeline
- Co Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
941. Structural Hazard:
- Ao An instruction in the pipeline needs a resource being used by another instruction in the pipeline
- Bo An instruction depends on a data value produced by an earlier instruction
- Co Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
9513. The formula of “Iron Law” of Processor Performance:
- Ao time/program = instruction/program * cycles/instruction * time/cycle
- Bo time/program = instruction/program * cycles/instruction + time/cycle
- Co time/program = instruction/program + cycles/instruction * time/cycle
9612. Algorithm for Cache MISS:
- Ao Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> Read block of data from main memory -> Replace victim block in cache with new block -> return copy of data from cache
- Bo Processor issues load request to cache -> Read block of data from main memory -> return copy of data from cache
- Co Processor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from cache
9711. Algorithm for Cache HIT:
- Ao Processor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from cache
- Bo Processor issues load request to cache -> Read block of data from main memory -> return copy of data from cache
- Co Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> return copy of data from cache
989. Capacity -
- Ao cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
- Bo misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
- Co first-reference to a block, occur even with infinite cache
998. Compulsory -
- Ao cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
- Bo first-reference to a block, occur even with infinite cache
- Co misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
1007. Average Memory Access Time is equal:
- Ao Hit Time * ( Miss Rate + Miss Penalty )
- Bo Hit Time - ( Miss Rate + Miss Penalty )
- Co Hit Time / ( Miss Rate - Miss Penalty )
- Do Hit Time + ( Miss Rate * Miss Penalty )
1016. Cache MISS:
- Ao No Write Allocate, Write Allocate
- Bo Write Through, Write Back
1025. Cache HIT:
- Ao No Write Allocate, Write Allocate
- Bo Write Through, Write Back
1034. What occurs at Data access when we speak about Common And Predictable Memory Reference Patterns?
- Ao subroutine call
- Bo n loop iterations
- Co vector access
1043. What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns?
- Ao subroutine call
- Bo n loop iterations
- Co vector access
1052. What occurs at Intruction fetches when we speak about Common And Predictable Memory Reference Patterns?
- Ao n loop iterations
- Bo subroutine call
- Co vector access
1061. - What is a Latency:
- Ao is time for a single access – Main memory latency is usually >> than processor cycle time
- Bo is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
- Co is amount of data that can be in flight at the same time (Little’s Law)
Informações
- Descrição
- Quiz sobre CSA IITU PART 2 (235), criado por Hello World em 20-12-2017.
- Autor
- Hello World
- Idioma
- English
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