Flashcards
03Handout01
Flashcards do conjunto (37)
- 1The original Verilog standard (IEEE 1364) has been updated numerous times since its creation in __.1995
- 2The most significant update occurred in 2001, which was titled___.IEEE 1394-2001
- 3In 2005 minor corrections and improvements were added to the standard, which resulted in ___IEEE 1394-2005
- 4describes a single system in a single file. The file has the suffix *.v. Within the file, the system description is contained within a module.Verilog design
- 5it includes the interface to the system (i.e., the inputs and outputs) and the description of the behaviormodule
- 6—
- 7Verilog Assignments• Structural Description
• Continuous Assignments
• Procedural Assignments
• Hierarchical Assignments - 8this description of a digital circuit consists of the interconnection of basic circuit elements like logic gates. Verilog includes basic gate-level primitives. A logic circuit is specified in the form of a module with inputs and outputs (ports) and statements that define the circuit. Note: Do not forget to add a semicolon (;) at the end of each expression.• Structural Description
- 9—
- 10—
- 11This is used to assign values onto scalar and vector nets that whenever the signal on the RHS (Right-hand-side) changes, the LHS (Light-hand-side) will be reevaluated. Note: Whenever variable “b” or “c” (in the LHS) changes, variable “a” (RHS) is updated instantly.• Continuous Assignments
- 12It represents structural connections between components/hardware elements.o Nets
- 13—
- 14It is computed as some point in time (ex: A clock) then has to get stored in a memory element. Rather than specifying conditional expressions, procedural statements (if-else, case, while, for statements) as a higher level of abstraction are used.Procedural Assignments
- 15represent variables used to store data. It retains value until another value is placed.o Registers
- 16—
- 17It is composed of the top-level module and several instances of lower-level modules which may contain sub-modules.• Hierarchical Assignments
- 18are instantiated in a higher-level module. The output of a lower-level module, as seen by the higher-level module, is a continuous assignment to a net. It implies that modules cannot be instantiated inside a procedural block such as the always block.o Lower-level modules
- 19—
- 20Data Types• Variable Data Types
• Vector
• Array
• Expressing Numbers Using Different Bases
• Parameter
• Compiler Directive - 21These data types model storage. Variable data types will hold the value assigned to them until their next assignment.• Variable Data Types
- 22—
- 23It refers to a one-dimensional array of elements. All of the net data types, in addition to the variable type reg, can be used to form vectors. While any range of indices can be used, it is common practice to have the LSB index start at zero.• Vector
- 24• Vector Example
- 25It refers to a multidimensional array of elements. This can also be thought of as a “vector of vectors.” Vectors within the array all have the same dimensions.• Array
- 26• Array Example
- 27If a number is simply entered into Verilog without identifying syntax, it is treated as an integer. Verilog supports defining numbers on other bases.• Expressing Numbers Using Different Bases
- 28• Expressing Numbers Using Different Bases Example
- 29constant, is useful for representing a quantity that will be used multiple times in the architecture. Note: the type is optional and can only be integer, time, real, or real-time. If a type is provided, the parameter will have the same properties as a variable of the same time. If the type is excluded, the parameter will take on the type of the value assigned to it.• Parameter
- 30Parameter ExampleExample:
parameter BUS_WIDTH = 64;
parameter NICKEL = 8’b0000_0101; - 31It provides additional information to the simulation tool on how to interpret the Verilog model. A compiler directive is placed before the module definition and is preceded with a backtick (i.e., `). Note: It is not an apostrophe.• Compiler Directive
- 32—
- 33Compiler Directive ExampleExample:
‘timescale 1ns/1ps
• Declares the unit of time is 1 ns with a precision of 1ps
• The precision is the smallest amount that the time can take on.
• For example, with this directive, the number 0.001 would be interpreted as 0.001 ns or 1 ps.
• However, the number 0.0001 would be interpreted as 0 since it is smaller than the minimum precision value. - 34This lets you insert the entire contents of a source file into another file during Verilog compilation. You can use the `include compiler directive to include global or commonly-used definitions and tasks, without encapsulating repeated code within module boundaries.`include
- 35This compiler directive is used for defining text MACROS. Since `define is a compiler directive, it can be used across multiple files.`define
- 36This defines the timescale of the delay unit and its smallest precision.`timescale ,
- 37This allows the user to override the ordinary default type (wire) of implicitly declared nets. It must be used outside a module.`defaultnettype
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- normal Intro to HDL FlashCards sobre 03Handout01, criado por Eljin Aguilar em 02-03-2025.
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- Eljin Aguilar
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