Chapter 7: Pipelining & RISC

Chapter 7: Pipelining & RISC

1. Pipelining

   • Allow the execution of multiple instruction to overlap in time.

2. Pipelining of unequal stages

   • Important for pipelining where stages are unequal :
     • Take the largest of the stage delay to b the cycle time.
       • No stage overlaps and latency must be constant
         • Ensure that instruction overlaptop is the same as the cycle time else get timing diagram is wrong

3. Pipeline hazards

   • Resource
     • Data
       • Control

4. Types of Data Hazard

   • Read after write (RAW), or true dependency
     • An instruction modifies a register or memory location. Succeeding instruction reads data in memory or register location. Hazard occurs if the read takes place before write operation is complete
       • Write after read (WAR), or antidependency. An instruction reads a register or memory location. Succeeding instruction writes to the location. Hazard occurs if the write operation completes before the read operation takes place
         • Write after write (WAW), or output dependency. Two instructions both write to the same location . Hazard occurs if the write operations take place in the reverse order of the intended sequence