ATmega128

ATmega128

1. Memories

   • Program
     • In-system Flash
       • 16k X 16 = 128kBytes
         • Application section
         • Boot section
   • Data
     • SRAM
       • Internal SRAM 4096 x 8
         • $0000-$001F = Register file
         • $0020-$005F = 64 I/O registers
         • $0060-$00FF = 160 Ext I/O regs.
         • $0100-$10FF
       • External SRAM 0-64k x 8
         • $1100-$FFFF
     • EEPROM

2. STATUS REGISTER - SREG

   • Bit 7 - I : Global Interrupt Enable
     • When an interrupt occurs, the I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a RETI is executed.
   • Bit 6 - T: Bit Copy Storage
   • Bit 5 - H : Half Carry Flag
   • Bit 4 - S : Sign Bit S= N + V
   • Bit 3 - V : Two's Complement Overflow Flag
   • Bit 2 - N : Negative Flag
   • Bit 1 - Z : Zero Flag
   • Bit 0 - C : Carry Flag

3. MCU Control Register - MCUCR

   • Bit 7 - SRE : Exernal SRAM/XMEM Enable
   • Bit 6 - SRW10 : Wait-state Select Bit
   • Bit 5 - SE : Sleep Enable
   • Bits 4..2 - SM2..0 : Sleep Mode

4. External Memory Control Register A - XMCRA

   • Bit 7 - Reserved Bit: WRITE TO ZERO!
   • Bits 6..4 - SRL2, SRL1, SRL0 : Wait-state Sector Limit
   • Bits 3..2 - SRW01, SRW00 : Wait-state Select Bits for Lower Sector
   • Bit 0 - Reserved: WRITE TO ZERO!

5. External Memory Control Register B - XMCRB

   • Bit 7 - XMBK : External memory Bus-keeper Enable
   • Bit 2..0 - XMM2, XMM1, XMM0 : External Memory High Mask

6. XTAL Divide Control Register - XDIV

   • Bit 7 - XDIVEN : XTAL Divide Enable
   • Bits 6..0 - XDIV6..XDIV0 : XTAL Divide Select Bits 6-0

7. Flash FUSE BITS

   • Clock
     • CKSEL3..0
     • SUT1..0 : Start-up time
     • CKOPT

8. MCU Control and Status Register - MCUCSR

   • Bit 4 - JTRF : JTAG Reset Flag
   • Bit 3 - WDRF : Watchdog Reset Flag
   • Bit 2 - BORF : Frown-out Reset Flag
   • Bit 1 - EXTRF : External Reset Flag
   • Bit 0 - PORF : Power-On Reset Flag
   • Bits 6..5 - Reserved

9. Watchdog Timer Control Register - WDTCR

10. PGIO

    • DDRxn : Data Direction Register of Port x and Pin n
      • 1
        • Pin n of Port x=output
      • 0
        • Pin n of Port x=input
    • PORTxn
      • 1
        • If DDRxn=1
          • PINxn = 1
        • If DDRxn = 0
          • Pull-Up resistor of Pin n of Port x is enabled
      • 0
        • If DDRxn=1
          • PINxn = 0
        • If DDRxn=0
          • Pull-Up resistor of Pin n of Port x is disabled
    • PINxn = Port x Pin n value - READ ONLY