Quiz
[CPSC313 Final] Unit 3 Memory
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Perguntas do quiz (80)
1Choose all the features that apply to SRAM (Static Random Access Memory)
- AStores each bit in a bistable memory cell
- B6 transistors
- CMore expensive than DRAM
- DPersistent
- EFaster than DRAM
- FStores each bit as charge on a capacitor
- GSensitive
- H1 Transistor
2Choose all the features that apply to DRAM (Dynamic Random Access Memory)
- AStores each bit in a bistable memory cell
- B6 transistors
- CMore expensive than SRAM
- DPersistent
- EFaster than SRAM
- FStores each bit as charge on a capacitor
- GSensitive
- H1 Transistor
3Build the Memory Hierarchy!
L0: [blank_start]Registers[blank_end]
L1: [blank_start]L1 cache[blank_end] ([blank_start]SRAM[blank_end])
L2: [blank_start]L2 cache[blank_end] (SRAM)
L3: [blank_start]Main memory[blank_end] ([blank_start]DRAM[blank_end])
L4: [blank_start]Local secondary storage[blank_end] ([blank_start]local disks[blank_end])
L5: [blank_start]Remote secondary storage[blank_end] (tapes, web servers, distributed file systems)
L0 to L2 is [blank_start]smaller, faster, costlier[blank_end] per byte
L3 to L5 is [blank_start]larger, slower, cheaper[blank_end] per byte- ARegisters
- BL0 cache
- CL1 cache
- DL2 cache
- ESRAM
- FRRAM
- GMain memory
- HDRAM
- IL3 Cache
- JLocal secondary storage
- KRemote secondary storage
- LL4 Cache
- ML5 Cache
- Nlocal disks
- Osmaller, faster, costlier
- Plarger, slower, cheaper
4The cells in a DRAM chip are partitioned into d [blank_start]supercells[blank_end], each consisting of w [blank_start]DRAM cells[blank_end] storing a total of dw [blank_start]bits of information[blank_end]. The supercells are organized as a rectangular array with r rows and c columns where [blank_start]rc = d[blank_end]. Each supercell has an address of the form (i, j) where i denotes the [blank_start]row[blank_end] and j denotes the [blank_start]column[blank_end].
- Asupercells
- BDRAM cells
- Cbits of information
- Dbytes of information
- Erc = d
- Fr + c = d
- Gc - r = d
- Hc/r = d
- Irow
- Jcolumn
5What are the specs of a 16 X 8 DRAM chip?
- A128 bits
16 Supercells (per DRAM cell)
8 bits per supercell
4 Rows
4 Columns - B64 bits
8 Supercells (per DRAM cell)
4 bits per supercell
2 Rows
2 Columns - C128 bytes
16 Supercells (per DRAM cell)
8 bytes per supercell
4 Rows
4 Columns - D64 bytes
8 Supercells (per DRAM cell)
4 bytes per supercell
2 Rows
2 Columns
- A128 bits
6In a 16 x 8 DRAM, how many bits are sent by the Memory Controller for each chip?
- A8
- B16
7Row access strobe requests and Column access strobe requests share the same DRAM address pin
- AVerdadeiro
- BFalso
8When reading an access of supercell (2,1), the memory controller sends [blank_start]row address 2[blank_end].
- Arow address 2
- Bcolumn address 2
- Crow address 1
- Dcolumn address 1
9In response to receiving a [blank_start]row address[blank_end], the DRAM copies the entire contents of that [blank_start]row[blank_end] into an [blank_start]internal row buffer[blank_end].
- Arow address
- Bcolumn address
- Crow
- Dcolumn
- Einternal row buffer
- Finternal column buffer
10Reference locality exists when data or code accesses tend to be near each other [blank_start]temporally[blank_end] or [blank_start]spatially[blank_end]
- Atemporally
- Bspatially
- Clocally
- Dsparingly
- Esparsely
- Fmoderately
- Gdensely
11[blank_start]Temporal[blank_end] locality exists when there are multiple accesses to the same memory within a short interval
- ATemporal
- BReferential
- CTrump
- DClinton
- ESpatial
12A [blank_start]cache hit[blank_end] happens when a particular data object from level k + 1 is found at level k.
- Acache hit
- Bcache miss
- Ccold miss
- Dcompulsory miss
13A [blank_start]cache miss[blank_end] happens when a data object d from level k +1 is not found.
- Acache miss
- Bcache hit
14When the cache is full and the cache at level k fetches the block d from the cache at level k + 1, it may overwrite an existing block if the level k cache is full. This is known as [blank_start]replacing/evicting[blank_end] the block. This block is sometimes referred to as the [blank_start]victim block[blank_end]. The decision about which block is replaced is governed by the cache's [blank_start]replacement policy[blank_end].
- Areplacing/evicting
- Bfetching
- Cpulling
- Dvictim block
- Ereplacee
- Flost block
- Greplacement policy
- Hrenewal policy
- Ieviction policy
- Jfetching policy
- Keject policy
15A least recently used policy would choose the block that
- Awas recently fetched
- Blast accessed furthest in the past
- Cwas recently evicted
- Dwas just used
16An empty cache is sometimes referred to as a cold cache. Misses that involve the cache at level k being empty are called cold misses or [blank_start]compulsory misses[blank_end].
- Acompulsory misses
- Bintentional misses
- Calways misses
- Dunavoidable misses
17In a placement policy that involves restricting blocks at k + 1 to a small subset of blocks at level k, we can encounter a miss where the cache is large enough to hold the referenced data objects, but because they map to the same cache block, the cache keeps missing. This type of miss is known as a [blank_start]conflict miss[blank_end].
- Aconflict miss
- Bintentional miss
- Ccompulsory miss
18If the working set exceeds the size of the cache, the cache will experience what are known as [blank_start]capacity misses[blank_end].
- Acapacity misses
19The compiler manages the register file.
- AVerdadeiro
- BFalso
20L1, L2, and L3 are managed by [blank_start]hardware logic[blank_end].
- Ahardware logic
- Bthe compiler
- Cthe memory bus
- DDRAM
- Ethe CPU
21Match the parameter to the corresponding label:
[blank_start]Fundamental Parameters[blank_end]
S: [blank_start]Number of sets[blank_end]
E: [blank_start]Number of lines per set[blank_end]
[blank_start]B[blank_end]: Block size (byte)
[blank_start]m[blank_end]: Number of physical (main memory) address bits
Derived quantities
[blank_start]M[blank_end]: Max number of unique memory addresses
s: [blank_start]Number of set index bits[blank_end]
[blank_start]b[blank_end]: Number of block offset bits
t: [blank_start]Number of tag bits[blank_end]
[blank_start]C[blank_end]: Cache size (bytes), not including overhead such as the valid and tag bits- AFundamental Parameters
- BB
- Cm
- DM
- Eb
- FC
- GNumber of sets
- HNumber of lines per set
- INumber of set index bits
- JNumber of tag bits
22Given the Maximum number of unique memory addresses (M), what could you tell me about a machine?
- AThe number of physical (main memory) address bits (m)
- BNumber of set index bits (s)
- CCache size (C)
- DNumber of sets (S)
23Given the number of lines per set (E), what could you tell me about a machine?
- ANumber of set index bits (s)
- BNumber of sets (S)
- CCache size (C)
- DNone of the above
24Given the block size (B) what could you tell me about a machine?
- ANumber of block offset bits (b)
- BNumber of set index bits (s)
- CNumber of tag bits (t)
- DCache size (C)
25Given the number of sets (S), block size (B), and the max number of unique memory addresses (M), what could you tell me about a machine?
- ANumber of set index bits
- BNumber of block offset bits
- CNumber of tag bits
- DNumber of physical (main memory) address bits
- ECache size
26Given the number of lines per set (E), the number of block offset bits (b), and the number of set index bits (s), what could you tell me about a machine?
- ABlock size (B)
- BNumber of sets (S)
- CCache size (C)
- DNumber of tag bits
- EMaximum number of unique memory addresses (M)
- FNumber of physical (main memory) address bits (m)
27Given a Cache size of 1024 bytes, a block size of 4 bytes, and 1 line per set, what are the number of sets?
[blank_start]1024 / (4*1)[blank_end]
Hint: C = [blank_start]B * E * S[blank_end]- A1024 / (4*1)
- B1024 / (4^2)
- C1024 - (4 + 1)
- D(1 + 1024) / 4
- E(4 + 1024) / 1
- FB * E * S
- G(B - E) * S
28Given a cache size of 1024, 32 address bits, a block size of 8 bytes, and 4 lines per set, what are the number of tag bits?
[blank_start]32 - ( (1024 / (4*8)) + log2(8) )[blank_end]
Hint: t = m - (s + b)- A32 - ( (1024 / (4*8)) + log2(8) )
- B1024 - ( (32 / (4*4)) + log2(8) )
- C1024 - ( (4 / (32*32)) + log2(4) )
- D32 - ( (32 / (4*8)) + log2(1024) )
29Caches are grouped into different classes based on [blank_start]E, the number of cache lines per set[blank_end]
- AE, the number of cache lines per set
- BS, the number of sets
- Cm, the number of physical address bits
- DB, the block size
30A direct-mapped cache has 1 line per set.
- AVerdadeiro
- BFalso
31The process that a cache goes through of determining whether a request is a hit or a miss and then extracting the requested word consists of three steps: (1) [blank_start]set selection[blank_end], (2) [blank_start]line matching[blank_end], (3) [blank_start]word extraction[blank_end]
- Aset selection
- Bcache selection
- Cline matching
- Dtag matching
- Eword extraction
- Fvalid bit check
32IN A DIRECT-MAPPED CACHE
Given w = memory word
Consider that the textbook gives a diagram for the w as follows:
|=Tag=|=Set index=|=Block offset=|
The following describes the set selection step:
(1) Cache extracts the [blank_start]s set index bits[blank_end] from the [blank_start]middle[blank_end] of the address for w
(2) Bits are interpreted as an [blank_start]unsigned integer set index[blank_end]- As set index bits
- Bb block offset bits
- Ct tag bits
- Dmiddle
- Estart
- Fend
- Gunsigned integer set index
- Hsigned integer set index
- Iunsigned integer block offset
- Jsigned integer block offset
- Kunsigned integer tag
- Lsigned integer tag
33IN A DIRECT-MAPPED CACHE
Given w = memory word and set i
The next step is to determine if a copy of the word w is stored in one of the cache lines contained in set i. A copy of w is contained in the line if and only if the [blank_start]valid bit[blank_end] is set AND the [blank_start]tag[blank_end] in the cache line matches the [blank_start]tag in the address[blank_end] of w.- Avalid bit
- Btag
- Ctag in the address
- Dblock offset in the address
- Eset index in the address
- Fset index
- Gblock offset
- Hblock offset bit
- Iset index bit
34IN A DIRECT-MAPPED CACHE
Given w = memory word
If we have a cache hit, we need to determine where the desired word starts in the block. The [blank_start]block offset bits[blank_end] provide us with the [blank_start]offset[blank_end] of the first byte in the desired word.- Ablock offset bits
- Btag bits
- Cset index bits
- Doffset
- Eset
- Ftag
35IN A DIRECT-MAPPED CACHE
Given w = memory word
If the cache misses, then it needs to retrieve the requested block from the next level in the memory hierarchy and store the new block in one of the cache lines of the set. If the set is full of valid cache lines, then one of the existing lines must be evicted. The replacement policy is "[blank_start]current line[blank_end] is replaced by the newly fetched line."- Acurrent line
- Bleast used
- Ca random line
- Dmost used
36The term [blank_start]thrashing[blank_end] describes any situation where a cache is repeatedly loading and evicting the same sets of cache blocks.
- Athrashing
- Bconflict miss
- Ccold miss
- Dcapacity miss
37Conflict misses in direct-mapped caches typically occur when programs access arrays who sizes are a power of 2.
- AVerdadeiro
- BFalso
38Given a four-set cache outlined thusly:
00 [xxxxxxxxx]
01 [xxxxxxxxx]
10 [xxxxxxxxx]
11 [xxxxxxxxx]
The best way to make use of this cache (or really any cache) is to use [blank_start]middle bit[blank_end] indexing such that addresses [blank_start]ARE NOT[blank_end] sorted by the set index so that [blank_start]alternating[blank_end] addresses can map to the cache.- Amiddle bit
- BARE NOT
- Calternating
- Dadjacent
- Ehigh-order bit
- Flow-order bit
- GARE
39A Set Associative Cache has [blank_start]1 < E < C/B[blank_end] so that each set holds [blank_start]more than one cache line[blank_end].
- A1 < E < C/B
- BE = C/B
- Cmore than one cache line
- Dall the cache lines
40IN SET ASSOCIATIVE CACHES
Set selection is identical to set selection in direct-mapped caches.- AVerdadeiro
- BFalso
41IN A SET ASSOCIATIVE CACHE
Line matching is more involved because the it must check the [blank_start]tags and valid bits of multiple lines[blank_end] in order to determine if the requested word is in the set. It does this by simply checking lines with [blank_start]valid bits[blank_end] for a [blank_start]tag[blank_end] that matches.- Avalid bits
- Btag
- Ctags and valid bits of multiple lines
- Dtags and valid bits of each line
42IN A SET ASSOCIATIVE CACHE
If we have a cache miss, the replacement policy determine what line gets evicted. Since it is difficult for programs to exploit replacement policies, the textbook only mentions a few that are used. These are:
[blank_start]Least frequently used (LFU) policy[blank_end] = evict line that has been referenced the least over a period of time
[blank_start]Least recently used (LRU) policy[blank_end] = evict line that was accessed furthest in the past
[blank_start]Random policy[blank_end] = choose victim block at random- ALeast frequently used (LFU) policy
- BLeast recently used (LRU) policy
- CRandom policy
43In our obligatory prison analogy, Bubba-Trap the Gunshow really wants to stab someone to re-establish his dominance as Underwarden. But he has a method to his madness.
He uses a [blank_start]LFU policy[blank_end] to justify stabbing Quiet Joe who is mentioned from time to time, but keeps his nose clean. Quiet Joe's life-threatening stab wound will warn the inmates that King Bubba-Trap thinks quiet people are [blank_start]suspicious as fuck[blank_end].
He uses a [blank_start]LRU policy[blank_end] to justify stabbing Old-man Geezer Samsonite who has seen better days during his life sentence for that accidental quadruple homicide of good senator McLeary's entire family with a faulty shotgun at a gunshow rally. King Bubba-Trap chooses him because it will teach other inmates that [blank_start]seniority doesn't mean shit[blank_end].
He uses a [blank_start]Random policy[blank_end] to justify stabbing a Sharron Marshall, a prison guard who just recently broke up with her lover over a spat about dishes. King Bubba-Trap chooses her because he rolled a D-20 and it rolled high. King Bubba-Trap is then [blank_start]shot[blank_end] by Sharron Marshall and dies. Go figure.- ALFU policy
- Bsuspicious as fuck
- CLRU policy
- Dseniority doesn't mean shit
- ERandom policy
- Fshot
- Gkissed
- Ha stitch in time saves nine
- Itoo loud
44Fully Associative Caches consist of [blank_start]a single set (E = C/B)[blank_end] [blank_start]that contains all of the cache lines[blank_end].
- Aa single set (E = C/B)
- Bmore than one set (1 < E < C/B)
- Cthat contains all of the cache lines
- Dthat each house multiple cache lines
45IN A FULLY ASSOCIATIVE CACHE
Set selection is [blank_start]trivial because there is only one set[blank_end].- Atrivial because there is only one set
- Bthe same as in a direct-mapped cache
- Cthe same as in a set associative cache
46IN A FULLY ASSOCIATIVE CACHE
Line matching/word selection [blank_start]works the same way as[blank_end] in a [blank_start]set associative cache[blank_end].- Aworks the same way as
- Bworks differently than
- Cset associative cache
- Ddirect-mapped cache
47It is [blank_start]difficult and expensive[blank_end] to build a fully associative cache that is both large and [blank_start]fast[blank_end] so they are typically reserved for [blank_start]smaller[blank_end] caches.
- Adifficult and expensive
- Beasy and cheap
- Cfast
- Dsmaller
- Ebigger
48A write hit is when we write a word w that is already cached
- AVerdadeiro
- BFalso
49The simplest approach to making sure that when a cache updates its copy of w, the next lower level of the hierarchy also does is known as [blank_start]write-through[blank_end] where w's cache block is immediately written to the next lower level.
A disadvantage to this approach is that it [blank_start]causes bus traffic[blank_end] with every write.- Acauses bus traffic
- Bcreates additional complexity
- Cwrite-through
- Dwrite-back
- Ewrite-allocate
- Fno-write-allocate
50Another approach, known as [blank_start]write-back[blank_end], defers the update as long as possible by writing the updated block to the next lower level only when it is [blank_start]evicted from the cache[blank_end] by the replacement algorithm.
This can significantly reduce [blank_start]bus traffic[blank_end], but it [blank_start]adds complexity[blank_end]. The cache must maintain an additional [blank_start]dirty bit[blank_end] for each cache line that indicates whether or not the cache block has been modified.- Awrite-back
- Bevicted from the cache
- Cadded to the cache
- Dwrite-through
- Ewrite-allocate
- Fno-write-allocate
- Gbus traffic
- Hcomplexity
- Iadds complexity
- Jincreases bus traffic
- Kdirty bit
- Ltag bit
- Mvalid bit
- Nblock offset bit
- Oset index bit
51When dealing with write misses, one approach called [blank_start]write-allocate[blank_end] loads the corresponding block from the [blank_start]next lower level[blank_end] into the cache and then updates the cache block.
This approach has the disadvantage that every miss results in [blank_start]a block transfer[blank_end] from the next lower level to the cache.- Awrite-allocate
- Bwrite-through
- Cno-write-allocate
- Dwrite-back
- Enext lower level
- Fnext higher level
- Ga block transfer
- Ha write hit
- Iextra bus traffic
52The alternative to write-allocate is known as [blank_start]no-write-allocate[blank_end]. It bypasses the cache and write the word directly to the [blank_start]next lower level[blank_end].
- Ano-write-allocate
- Bnext lower level
- Ccache
- Dwrite-through
- Ewrite-back
53Write-through caches are typically [blank_start]no-write-allocate[blank_end]. Write-back caches are typically [blank_start]write-allocate[blank_end].
- Ano-write-allocate
- Bwrite-allocate
54Instructions that hold only instructions are called [blank_start]i-caches[blank_end] and ones that hold only program data are [blank_start]d-caches[blank_end]. Ones that hold both are [blank_start]unified caches[blank_end].
- Ai-caches
- Bins-caches
- Cd-caches
- Dda-caches
- Eunified caches
- Fu-caches
- Guni-caches
55i-caches are typically write only caches.
- AVerdadeiro
- BFalso
56Caches performance is evaluated with the following metrics:
- AMiss rate
- BHit rate
- CHit time
- DHit penalty
- EMiss penalty
- FMiss time
57Miss rate is the fraction of memory references during the execution of a program/part of a program that miss. Miss rate is computed as [blank_start]#misses / #references[blank_end].
- A#misses / #references
- B1 - miss penalty
58Hit rate is the fraction of memory references that hit. It is computed as [blank_start]1 - miss rate[blank_end].
- A1 - miss rate
- B#hits/miss-penalty
59Hit time is the time it takes to deliver a word including set [blank_start]selection[blank_end], [blank_start]line identification[blank_end], and [blank_start]word[blank_end] selection.
- Aselection
- Bword
- Cset
- Daquisition
- Eline identification
- Fset selection
- Gword selection
60Miss penalty is any additional time required because of a [blank_start]miss[blank_end].
- Amiss
- Bwrite-through
- Cwrite-back
- Dwrite-allocate
- Eno-write-allocate
61Larger cache sizes will
- Aincrease hit rate
- Bdecrease hit rate
- Cincrease hit time
- Ddecrease hit time
62Larger block sizes
- Aincrease hit rate
- Bdecrease hit rate
- Cpossibly decrease hit rate in programs with more temporal locality
- Dincreased miss penalty
- Edecreased miss penalty
63Higher associativity
- Adecreases thrashing due to conflict misses
- Bis expensive to implement and hard to make fast
- Cincreases hit time
- Dincreases miss penalty
- Edecreases hit time
- Fdecreases miss penalty
64Write-through caches are [blank_start]simpler to implement[blank_end] and can use a [blank_start]write buffer[blank_end] that works independently of the cache to update memory. [blank_start]Read misses[blank_end] are also less expensive because they do not trigger a memory write.
Write-back caches result in [blank_start]fewer transfers[blank_end] which allows more bandwidth to memory for I/O devices that perform DMA, whatever the fuck that is. This is important as we move down the hierarchy where [blank_start]transfer times increase[blank_end].- Asimpler to implement
- Bwrite buffer
- CRead misses
- Dfewer transfers
- Etransfer times increase
- Ftransfer times decrease
- Gmore transfers
- HWrite misses
- Iread buffer
- Jharder to implement
65The rate that a program reads data from the memory system is called [blank_start]read throughput[blank_end] or sometimes the [blank_start]read bandwidth[blank_end]. Typically expressed in units of [blank_start]MB/s[blank_end]
- AMB/s
- Bb/s
- Ckb/s
- Dread bandwidth
- Eread-speed
- Fwrite-speed
- Gread throughput
- Hwrite throughput
- Iread scylla
66A memory mountain is a 3D-graph showing [blank_start]read throughput[blank_end] as a function of [blank_start]temporal & spatial locality[blank_end]. It's axis are [blank_start]read throughput,[blank_end] [blank_start]stride[blank_end], and [blank_start]size.[blank_end]
- Aread throughput
- Bread throughput,
- Cstride
- Dsize.
- Ewrite throughput
- Fwrite throughput,
- Gridges
- Htemporal locality
- Ispatial locality
- Jslopes
- Kbytes.
- Lmegabytes.
- Mgigabytes per second.
- Ntemporal & spatial locality
67What performance impact(s) would you expect would be directly caused by increasing block size without changing cache size or associativity, for some workloads.
- AMore cold misses
- BFewer cold misses
- CMore capacity misses
- DFewer capacity misses
- EMore conflict misses
- FFewer conflict misses
- GLower cache hit latency
- HHigher cache hit latency
68What performance impact(s) would you expect would be directly caused by increasing associatibity without changing cache size or block size, for some workloads.
- AMore cold misses
- BFewer cold misses
- CFewer conflict misses
- DMore conflict misses
- EMore capacity misses
- FFewer capacity misses
- GLower cache hit latency
- HHigher cache hit latency
69What performance impact(s) would you expect would be directly caused by increasing cache sise without changing associativity or block size, for some workloads.
- AMore cold misses
- BFewer cold misses
- CMore conflict misses
- DFewer conflict misses
- EMore capacity misses
- FFewer capacity misses
- GLower cache hit latency
- HHigher cache hit latency
70Match the term with its definition.
[blank_start]cache block[blank_end] = data from memory that is stored as a unit in the cache
[blank_start]cache line[blank_end] = portion of a cache unit that includes a single valid-bit and tag
[blank_start]cache set[blank_end] = portion of cache that stores multiple valid-bits and tags.
[blank_start]tag[blank_end] = part of an address that is stored in the cache
[blank_start]index[blank_end] = part of an address that selects a specific portion of the cache for access
[blank_start]offset[blank_end] = part of an address that selects a specific portion of a cache block- Acache block
- Bcache line
- Ccache set
- Dtag
- Eindex
- Foffset
71Compare two caches the differ only in which address bits are used for the index and tag. In one cache the high-order bits are used for the tag and in the other the high-order bits are used for the index (recall the the higher-order part of a number is on the left).
What would be true of the cache that uses high-order bits for the INDEX?- AIt would have more conflict misses for workloads with spatial locality, but might have fewer conflict misses for workloads that access multiple items that have similar alignment.
- BIt would have more conflict misses but fewer capacity misses.
- CThe number of misses would be about the same.
- DIt would be worse in every way.
- EIt would be better in every way.
72Consider a 16-MB, 8-way set associative cache with 64-B blocks. If addresses are 32-bits long, how many address bits are used for the cache tag: [tag], index: [index], offset: [offset]?
To be correct your answer must contain only digits (i.e., 0..9) and no leading zeros.
You might find it useful to know that 16-MB = 2^24 B, that 64-B = 2^6 B, and that 8 = 2^3.
tag = [blank_start]11[blank_end]
index = [blank_start]15[blank_end]
offset = [blank_start]6[blank_end]- A11
- B15
- C6
73Consider that same 16-MB, 8-way set associative cache with 64-B blocks.
What is the value of the tag: [tag], index: [index], and offset: [offset] for the address 0x12345678?
To be correct your answer must contain only hex digits (i.e., 0..9,a-f), no leading zeros. Do not include the '0x' part.
tag = [blank_start]91[blank_end]
index = [blank_start]5159[blank_end]
offset = [blank_start]38[blank_end]- A91
- B5159
- C38
74Match the cache change to its effect on performance.
[blank_start]Increasing associativity[blank_end] = Fewer conflict misses, but higher hit latency
[blank_start]Increasing block size[blank_end] = Fewer cold misses, but more capacity misses.
[blank_start]Increasing cache size[blank_end] = Fewer capacity misses, but higher hit latency.
Write-back instead of write-through with write buffer = [blank_start]Lower write bandwidth[blank_end] (in some parts of hierarchy), but [blank_start]higher write miss latency[blank_end].- AIncreasing associativity
- BIncreasing block size
- CIncreasing cache size
- DLower write bandwidth
- Ehigher write miss latency
- FHigher write bandwidth
- Glower write miss latency
75Consider a 32-MB, 4-way set associative cache with 64-B blocks. (You may find it convenent to know that 32-MB is 2^25 and that 64 is 2^6).
GIVE YOUR ANSWER USING THE DIGITS 0..9; NO LEADING 0; NO OTHER CHARACTERS; IN BASE 10.
How many sets in this cache? Give your answer as the log-base-2 of this value (e.g., if the cache has 128 sets, give the answer 7).
[blank_start]17[blank_end]- A17
76Consider a 32-MB, 4-way set associative cache with 64-B blocks in a system with 32-bit addresses. (You may find it convenent to know that 32-MB is 2^25 and that 64 is 2^6).
GIVE YOUR ANSWER USING THE DIGITS 0..9; NO LEADING 0; NO OTHER CHARACTERS; IN BASE 10.
How many lines in this cache? Give your answer as the log-base-2 of this value (e.g., if the cache has 128 sets, give the answer 7).
[blank_start]19[blank_end]- A19
77In cache where 4 bits are used for the block offset and 8 bits for the index and where addresses are 32 bits.
For the address 0xa3cf74, what is value of the tag [tag], index [index], and block offset [offset].
GIVE YOUR ANSWERS USING THE DIGITS 0..9, a..f; NO LEADING 0; NO OTHER CHARACTERS; IN BASE 16.
tag = [blank_start]a3c[blank_end]
index = [blank_start]f7[blank_end]
offset = [blank_start]4[blank_end]- Aa3c
- Bf7
- C4
78Consider these two alternate loops for accessing the two-dimensional array int a[64][64], labeled A and B.
A:
for (int r=0; r<64; r++)
for (int c=0; c<64; c++)
s += a[r][c]
B:
for (int c=0; c<64; r++)
for (int r=0; r<64; c++)
s += a[r][c]
Which of the following statements best describes the difference between A and B.- AA will always have more cache hits than B.
- BB will always have more cache hits than A.
- CA will sometimes have more cache hits than B.
- DB will sometimes have more cache hits than A.
- EThey will tend to have the same number of cache hits under all circumstances.
- FNone of the above.
79Consider the following code that access an array.
for (int i=0; i<LEN*STRIDE; i+=STRIDE)
s += a[i]
Which of the follow statements best describes what you would expect to when STRIDE is increased?- AIt is not possible to tell from the information given.
- BFewer conflict misses.
- CFewer capacity misses.
- DFewer cold misses.
- EMore conflict misses.
- FMore capacity misses.
- GMore cold misses.
80What is the organization of the Write Buffer?
- AFully associative
- BDirect Mapped
- CSet associative
- DNone of the above
Informações
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- For those days when you need a lobotomy
- Autor
- Zim Brightwood
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- English
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