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PC Architecture Endterm
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Questions in this quiz (66)
11. In 32-bit addressing mode, address field is either 1 byte or?
- Ao 4 bytes
- Bo 2 bytes
- Co 6 bytes
22. If a block can be placed at every location in cache, this cache is said to be?
- Ao Fully associative
- Bo Directly mapped
- Co Indirectly mapped
33. Information when is written in cache, both to block in cache and block present in lower-level memory, refers to?
- Ao Write-through
- Bo Write-back
- Co Miss rate
44. Average access time of memory for having memory-hierarchy performance is given as?
- AAverage memory access time = Hit time - Miss rate
- Bo average memory access time = hit time + (miss rate and miss penalty)
- Co Average memory access time = Hit time + Miss rate - Miss penalty
55. As segment or a page is normally used for block, page-fault and address-fault is used for
- AHit
- Bo Miss
- Co Cache
- Do Stack
66. Virtual memory producing virtual-addresses, are translated by
- ALogical addresses
- Bo Physical addresses
- Co Local addresses
- Do All above
77. Per memory reference, miss-rate can be turned into per instruction misses rate by
- Ao Miss rate= Memory accesses* instructions
- Bo Miss rate= Memory accesses/ instructions
- Co Miss rate= Memory accesses-instructions
- Do Miss rate= Memory accesses+ instructions
88. Cutting of physical-memory into form of blocks and allocating them to different processes, stated technique is known as
- ARead back
- Bo Cache miss
- Co Virtual memory
- Do Cache hit
99. For reducing frequency on replacement of write-back blocks, commonly used feature, is known as
- AHit miss
- Bo Index field
- Co Dirty bit
- Do Write-through
1010. If cache is not able for containing all blocks needed while execution, miss is then known as
- Ao Hit miss
- Bo Cache hit
- Co Cache miss (capacity miss)
- Do Hit rate
11For completing programmer's desire for unlimited quick memory, suggested economical solution was
- Ao Memory hierarchy
- BTemporal locality
- CSpatial locality
1212. An instruction that does no operation for changing state is known as
- ANope
- Bo No
- Co NOP
1313. Set of instructions examined as candidates for potential execution is called the
- AFrame
- Bo Cube
- Co Window
1414. Different types of parallelism in applications like:
- Ao Data-Level Parallelism o Task-Level Parallelism (for applications)
- Bo Instruction-Level Parallelism (for computer hardware)
- Co All above
1515. Term 'computer architecture' is sometimes referred only to
- Ao Instruction set design
- Bo Circuit design
- Co Hardware design
16General categories of instructions' operation are
- Ao Data transfer
- Bo Arithmetic logical
- Co floating point
- Do All above
1717. The effectiveness of the cache memory is based on the property of
- Ao Locality of reference
- Bo Memory localization
- Co Memory size
1818. The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called _______.
- Ao Level 2 cache
- Bo Level 1 cache
- Co Registers
1919. The last on the hierarchy scale of memory devices is ______.
- Ao Main memory
- Bo Branch
- CSecondary memory
20In the memory hierarchy, as the speed of operation increases the memory size also increases
- ATrue
- BFalse
2121. A common measure of performance is
- Ao Price/performance ratio.
- Bo Performance/price ratio
- Co Operation/price ratio.
22The number successful accesses to memory stated as a fraction is called as _____
- Ao Miss rate
- Bo Hit rate
- Co Access rate
23With respect to changing among states of accomplishment and interruption, a measure of continuous service-accomplishment, is known as
- Ao Scalability
- Bo Module availability
- Co Module reliability
2424. From a reference initial instant, a measure of service accomplishment. is known as
- Ao Module reliability
- Bo Hardware
- Co Sector
2525. To initialize any port as an output port what value is to be given to it?
- Ao 0xFF
- Bo 0x00
- Co 0x01
- DA port is by default an output port
2626. In AVR, which registers are there for the I/O programming of ports?
- Ao all above
- Bo PORT
- Co PIN
- Do DDR
2727. The data will not go from the port registers to the pin unless:
- Ao DDR register of that port is set to 0
- Bo DDR register of that port is set to 1
- CPORT register of that port is set to 0
2828. What is the file extension that is loaded in a micro controller for executing any instruction?
- Ao .doc
- Bo .hex
- Co .txt
2929. What type of coherence misses is - that arise from the communication of data through the cache coherence mechanism?
- Ao True sharing misses
- Bo False sharing misses
3030. What type of coherence misses is - that arises from the use of an invalidation based coherence algorithm with a single valid bit per cache block?:
- Ao False sharing misses
- Bo True sharing misses
3131. At Directory-Based Cache Coherence Protocols: The Basics, which state in the following called “Shared” in a simple protocol?
- Ao One or more processors have the block cached, and the value in memory is up to date
- Bo Exactly one processor has a copy of the cache block, and it has written the block, so the memory copy is out of date
- Co No processor has a copy of the cache block
3232. At Directory-Based Cache Coherence Protocols: The Basics, which state in the following called “Modified” in a simple protocol?
- Ao No processor has a copy of the cache block
- Bo Exactly one processor has a copy of the cache block, and it has written the block, so the memory copy is out of date
- Co One or more processors have the block cached, and the value in memory is up to date
3332**. At Directory-Based Cache Coherence Protocols: The Basics, which state in the following called “Uncached” in a simple protocol?
- Ao No processor has a copy of the cache block
- Bo Exactly one processor has a copy of the cache block, and it has written the block, so the memory copy is out of date
- Co One or more processors have the block cached, and the value in memory is up to date
3433. In Non-Blocking Caches what does mean “Early restart”?
- Ao Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
- Bo Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
35What occurs at Instruction fetches when we speak about Common And Predictable Memory Reference Patterns?
- An loop iterations
- Bo subroutine call
- Cvector access
3636. What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns?
- Ao subroutine call
- Bo n loop iterations
- Co vector access
37What occurs at Data access when we speak about Common And Predictable Memory Reference Patterns?
- Ao subroutine call
- Bo n loop iterations
- Co vector access
3838. What is kernel process?
- Ao Provide at least two modes, indicating whether the running process is a user process or an operating system process
- Bo Provide at least five modes, indicating whether the running process is a user process or an operating system process
- Co Provide a portion of the processor state that a user process can use but not write
- Do None of them
3939. Which one is NOT concerning to pitfall?
- Ao Predicting cache performance of one program from another
- Bo Simulating enough instructions to get accurate performance measures of the memory hierarchy
- Co Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
- Do Over emphasizing memory bandwidth in DRAMs
4040. Which one is concerning to fallacy?
- Ao Predicting cache performance of one program from another
- Bo Simulating enough instructions to get accurate performance measures of the memory hierarchy
- Co Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
- Do Over emphasizing memory bandwidth in DRAMs
4143. At VLIW Speculative Execution, which of this solution is true about problem:
Branches restrict compiler code motion?- Ao Speculative operations that don’t cause exceptions
- Bo Hardware to check pointer hazards
4244. At VLIW Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
- Ao Hardware to check pointer hazards
- Bo Speculative operations that don’t cause exceptions
4345. At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches:
- Ao Allow one instruction to branch multiple directions
- Bo Speculative operations that don’t cause exceptions
4446. In Multilevel Caches “Local miss rate” equals =
- Ao misses in cache / accesses to cache
- Bo misses in cache / CPU memory accesses
- Co misses in cache / number of instructions
4547. In Multilevel Caches “Global miss rate” equals =
- Ao misses in cache / CPU memory accesses
- Bo misses in cache / accesses to cache
- Co misses in cache / number of instructions
4648. In Multilevel Caches “Misses per instruction” equals =
- Ao misses in cache / number of instructions
- Bo misses in cache / accesses to cache
- Co misses in cache / CPU memory accesses
4750. The time between the start and the completion of an event ,such as milliseconds for a disk access is...
- Ao latency
- Bo bandwidth
- Co throughput
- Do performance
4851. Total amount of work done in a given time , such as megabytes per second for disk transfer...
- Ao bandwidth (throughput)
- Bo latency
- Co performance
4952. Products that are sold by multiple vendors in large volumes and are essentially identical
- Ao commodities
- Bo boxes
- Co folders
- Do files
5053. Integrated circuit processes are characterized by the
- Ao feature size
- Bo permanent size n
- Co complex size
- Do fixed size
5154. Manufacturing costs that decrease over time are ____
- Ao the learning curve
- Bo the cycled line
- Co the regular option
- Do the final loop
5255. Volume is a ________ key factor in determining cost.
- Ao second
- Bo first
- Co fifth
- Do third
5356. The most companies spend only ____________ of their income on R&D, which includes all engineering.
- Ao 4% to 12%
- Bo 15% to 30%
- Co 1% to 17%
- Do 30% to 48%
5457. Desktop benchmarks divide into __ broad classes:
- Ao two
- Bo three
- Co four
- Do five
5558. A widely held rule of thumb is that a program spends __ of its execution time in only __ of the code.
- Ao 90% 10%
- Bo 50% 50%
- Co 70% 30%
- Do 89% 11%
5659. (Performance for entire task using the enhancement when possible) / (Performance for entire task without using the enhancement) is equals to:
- Ao Speedup
- Bo Efficiency
- Co Probability
- Do Ration
5760. Which of the following descriptions corresponds to static power?
- Ao Grows proportionally to the transistor count (whether or not the transistors are switching)
- Bo Proportional to the product of the number of switching transistors and the switching rate Probability
- Co Proportional to the product of the number of switching transistors and the switching rate
- Do All of the above
58If we want to sustain four instructions per clock
- Ao We must fetch more, issue more, and initiate execution on more than four instructions
- Bo We must fetch less, issue more, and initiate execution on more than two instructions
- Co We must fetch more, issue less, and initiate execution on more than three instructions
- Do We must fetch more, issue more, and initiate execution on less than five instructions
5962. What is a hash table?
- Ao Popular data structure for organizing a large collection of data items so that one can quickly answer questions
- Bo Popular data structure for updating large collections, so that one can hardly answer questions
- Co Popular tables for organizing a large collection of data structure
- Do Popular data structure for deletingsmall collections of data items so that one can hardly answer questions
6063. How this process called: “Operations execute as soon as their operands are available”
- Ao data flow execution
- Bo instruction execution
- Co data control execution
- Do instruction field execution
6164. For what the reorder buffer is used :
- Ao To pass results among instructions that may be speculated.
- Bo To pass parameters through instructions that may be speculated
- Co To get additional registers in the same way as the reservation stations
- Do To control registers
6265. Which one is not the major flavor of Multiple-issue processors:
- Ao statistically superscalar processors
- Bo dynamically scheduled superscalar processors
- Co statically scheduled superscalar processors
- Do VLIW (very long instruction word) processors
6366. Examples of superscalar(static):
- Ao MIPS and ARM
- Bo Pentium 4, MIPS R12K, IBM, Power5
- Co Itanium
- Do TI C6x
6467. Examples of superscalar(dynamic) :
- Ao None at the present
- Bo Pentium 4, MIPS R12K, IBM, Power5
- Co MIPS and ARM
- Do TI C6x
6568. Examples of VLIW processor:
- Ao TI C6x
- Bo MIPS and ARM
- Co Itanium
- Do Pentium 4, MIPS R12K, IBM, Power5
6669. Which is not the function of integrated instruction fetch unit:
- Ao Instruction memory commit
- Bo Integrated branch prediction
- Co Instruction prefetch
- Do Instruction memory access and buffering
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- ZIS SHIT IS SHIT
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- Created on 13 May 2018 · updated on 13 May 2018
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