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PCA_Final [arc2-1, Part-2]

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Arxitektura - gavno
Good Guy Beket
Quiz by Good Guy Beket, updated more than 1 year ago
Good Guy Beket
Created by Good Guy Beket almost 6 years ago
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Resource summary

Question 1

Question
What is a Latency:
Answer
  • is time for a single access – Main memory latency is usually >> than processor cycle time
  • is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
  • is amount of data that can be in flight at the same time (Little’s Law)

Question 2

Question
What occurs at Intruction fetches when we speak about Common And Predictable Memory Reference Patterns?
Answer
  • n loop iterations
  • subroutine call
  • vector access

Question 3

Question
What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns?
Answer
  • subroutine call
  • n loop iterations
  • vector access

Question 4

Question
What occurs at Data access when we speak about Common And Predictable Memory Reference Patterns?
Answer
  • subroutine call
  • n loop iterations
  • vector access

Question 5

Question
Cache HIT:
Answer
  • No Write Allocate, Write Allocate
  • Write Through, Write Back

Question 6

Question
Cache MISS:
Answer
  • No Write Allocate, Write Allocate
  • Write Through, Write Back

Question 7

Question
Average Memory Access Time is equal:
Answer
  • Hit Time * ( Miss Rate + Miss Penalty )
  • Hit Time - ( Miss Rate + Miss Penalty )
  • Hit Time / ( Miss Rate - Miss Penalty )
  • Hit Time + ( Miss Rate * Miss Penalty )

Question 8

Question
The formula of “Iron Law” of Processor Performance:
Answer
  • time/program = instruction/program * cycles/instruction * time/cycle
  • time/program = instruction/program * cycles/instruction + time/cycle
  • time/program = instruction/program + cycles/instruction * time/cycle

Question 9

Question
Structural Hazard:
Answer
  • An instruction in the pipeline needs a resource being used by another instruction in the pipeline
  • An instruction depends on a data value produced by an earlier instruction
  • Whether or not an instruction should be executed depends on a control decision made by an earlier instruction

Question 10

Question
Data Hazard:
Answer
  • An instruction depends on a data value produced by an earlier instruction
  • An instruction in the pipeline needs a resource being used by another instruction in the pipeline
  • Whether or not an instruction should be executed depends on a control decision made by an earlier instruction

Question 11

Question
Control Hazard:
Answer
  • Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
  • An instruction depends on a data value produced by an earlier instruction
  • An instruction in the pipeline needs a resource being used by another instruction in the pipeline

Question 12

Question
What is a Bandwidth:
Answer
  • a is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
  • is time for a single access – Main memory latency is usually >> than processor cycle time
  • is amount of data that can be in flight at the same time (Little’s Law)

Question 13

Question
What is a Bandwidth-Delay Product:
Answer
  • is amount of data that can be in flight at the same time (Little’s Law)
  • is time for a single access – Main memory latency is usually >> than processor cycle time
  • is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle

Question 14

Question
What is Computer Architecture?
Answer
  • is the design of the abstraction/implementation layers that allow us to execute information processing applications efficiently using manufacturing technologies
  • is a group of computer systems and other computing hardware devices that are linked together through communication channels to facilitate communication and resource-sharing among a wide range of users
  • the programs used to direct the operation of a computer, as well as documentation giving instructions on how to use them

Question 15

Question
Least Recently Used (LRU):
Answer
  • cache state must be updated on every access
  • Used in highly associative caches
  • FIFO with exception for most recently used block(s)

Question 16

Question
Cache Hit -
Answer
  • Write Through – write both cache and memory, generally higher traffic but simpler to design
  • Write cache only, memory is written when evicted, dirty bit per block avoids unnecessary write backs, more complicated
  • No Write Allocate – only write to main memory

Question 17

Question
Reduce Miss Rate: Large Cache Size. Empirical Rule of Thumb:
Answer
  • If cache size is doubled, miss rate usually drops by about √2
  • Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
  • None of them

Question 18

Question
Reduce Miss Rate: High Associativity. Empirical Rule of Thumb:
Answer
  • Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
  • If cache size is doubled, miss rate usually drops by about √2
  • None of them

Question 19

Question
What is the access time?
Answer
  • Time between when a read is requested and when the desired word arrives
  • The minimum time between requests to memory.
  • Describes the technology inside the memory chips and those innovative, internal organizations
  • None of them

Question 20

Question
What is the cycle time?
Answer
  • The minimum time between requests to memory.
  • Time between when a read is requested and when the desired word arrives
  • The maximum time between requests to memory.
  • None of them

Question 21

Question
What does SRAM stands for?
Answer
  • Static Random Access memory
  • System Random Access memory
  • Short Random Access memory
  • None of them

Question 22

Question
What does DRAM stands for?
Answer
  • Dynamic Random Access memory
  • Dual Random Access memory
  • Dataram Random Access memory

Question 23

Question
Which one is concerning to fallacy?
Answer
  • Predicting cache performance of one program from another
  • Simulating enough instructions to get accurate performance measures of the memory hierarchy
  • Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
  • Over emphasizing memory bandwidth in DRAMs

Question 24

Question
Which one is NOT concerning to pitfall?
Answer
  • Predicting cache performance of one program from another
  • Simulating enough instructions to get accurate performance measures of the memory hierarchy
  • Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
  • Over emphasizing memory bandwidth in DRAMs

Question 25

Question
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time” - ?
Answer
  • The time between when the user enters the command and the complete response is displayed
  • The time for the user to enter the command
  • The time from the reception of the response until the user begins to enter the next command

Question 26

Question
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time” - ?
Answer
  • The time from the reception of the response until the user begins to enter the next command
  • The time for the user to enter the command
  • The time between when the user enters the command and the complete response is displayed

Question 27

Question
Little’s Law and a series of definitions lead to several useful equations for “Time server” -
Answer
  • Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
  • Average time per task in the queue
  • Average time/task in the system, or the response time, which is the sum of Time queue and Time server

Question 28

Question
Little’s Law and a series of definitions lead to several useful equations for “Time queue” -
Answer
  • Average time per task in the queue
  • Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
  • Average time/task in the system, or the response time, which is the sum of Time queue and Time server

Question 29

Question
Little’s Law and a series of definitions lead to several useful equations for “Time system” -
Answer
  • Average time/task in the system, or the response time, which is the sum of Time queue and Time server
  • Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
  • Average time per task in the queue

Question 30

Question
Little’s Law and a series of definitions lead to several useful equations for “Length server” -
Answer
  • Average number of tasks in service
  • Average length of queue

Question 31

Question
Little’s Law and a series of definitions lead to several useful equations for “Length queue” -
Answer
  • Average length of queue
  • Average number of tasks in service

Question 32

Question
Select two-dimensional interconnection network
Answer
  • Mesh
  • Linear Array
  • Cross Bar

Question 33

Question
Select multi-dimensional interconnection network
Answer
  • Linear Array
  • Cross Bar
  • Cube

Question 34

Question
Select multi-dimensional interconnection network
Answer
  • Linear Array
  • Cross Bar
  • Hyper Cube
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