Quiz
Untitled
Create a free account to finish this quiz
Save your progress and see your final score.
Already have an account? Sign in
Questions in this quiz (102)
1Convert this number systems: DEC(9578) to HEX?
- A• 256A
- B• 43B1
- C• 7DE1
- D• A31F
2Convert this number systems: DEC(9845) to HEX?:
- A• 2675
- B• 2798
- C• 2945
- D• 2811
3 Convert this number systems: DEC(4591) to OCT?:
- A• 10757
- B• 12832
- C• 11543
- D• 13531
4Convert this number systems: DEC(5123) to OCT?:
- A• 12003
- B• 13456
- C• 14512
- D• 10602
5Convert this number systems: DEC(4812) to OCT?:
- A• 11314
- B• 12012
- C• 13712
- D• 10514
6How many parts of Memory Hierarchy
- A4
- B3
- C5
- D2
7In Memory Hierarchy, at the Outboard storage which of the following are included:
- A• Cache
- B• Main memory
- C• Magnetic tape
- D• Magnetic disk
8In Memory Hierarchy, at the Off-line storage which of the following are included:
- A• Cache
- B• Magnetic disk
- C• Magnetic tape
- D• Main memory
9In Memory Hierarchy, at the Inboard storage which of the following are included:
- A• Main memory
- B• Magnetic disk
- C• Magnetic tape
- D• Optical disk
10Cache Design has these properties?
- A• Size, block size, mapping function, replacement algorithm, write policy
- B• Size, search function, write function, read policy, vector algorithm
- C• Size, mapping algorithm, vector function, write policy, replacement function
- D• Size, blocking algorithm, search function, replacement vector, read policy
11Three techniques are possible for I/O operations:
- A• Programmed I/O, Interrupt-driven I/O, Direct memory access(DMA)
- B• Object-oriented I/O, Design I/O, Usable I/O
- C• Machine I/O, Architecture I/O, Hardware I/O
- D• Control I/O, Status I/O, Transfer I/O
12How many principles has Deadlock?
- A3
- B5
- C6
- D2
13Which of the following principles has Deadlock?
- A• Prevention, Avoidance, Detection
- B• Execution, Association, Starvation
- C• Exclusion, Avoidance, Starvation
- D• Starvation, Detection, Exclusion
14Much of the work in security and protection as it relates to operating systems can be roughly grouped into four categories?
- A• Availability, confidentiality, data integrity, authenticity
- B• Safety, accountability, reliability, density
- C• Usability, integrity, confidentiality, reliability
- D• Flexibility, availability, accountability, authenticity
15The central themes of operating system design are all concerned with the management of processes and threads?
- A• Multiprogramming, multiprocessing, distributed processing
- B• Multitasking, multiprogramming, multithreading
- C• Multiprocessing, uniprocessing, multitasking
- D• Multithreading, distributed processing, uniprocessing
16Can you solve the Dining Philosophers’ Problem using monitors?
- A• Yes
- B• No
- C• Yes, but only if there are less than five philosophers
- D• No, unless there are more than five philosophers
17Assembly line operation is also called as?
- A• Superscalar operation
- B• Pipelining process
- C• Von Neumann cycle
- D• None of the mentioned
18The CISC stands for?
- A• Computer Instruction Set Compliment
- B• Complete Instruction Set Compliment
- C• Computer Indexed Set Components
- D• Complex Instruction Set Computer
19The secondary effect that results from instruction scheduling in large code segments is called ___?
- A• Aggressive instruction
- B• Correlating predictors
- C• Register predictors
- D• Register pressure
20How many instructions can be implemented in MIPS?
- A• 2 clock cycles
- B• 3 clock cycles
- C• 4 clock cycles
- D• 5 clock cycles???
21What do you call the given statement as “The number successful accesses to memory stated as a fraction.”
- A• Hit rate
- B• Miss rate
- C• Success rate
- D• Access rate
22Of the following, identify the memory usually written by the manufacturer.
- A• RAM
- B• DRAM
- C• SRAM
- D• ROM
- ECash Memory
23 The Sun micro systems processors usually follow ___ architecture.
- A• CISC
- B• ISA
- C• ULTRA SPARC
- D• RISC
24The iconic feature of the RISC machine among the following are
- A• Reduced number of addressing modes
- B• Increased memory size
- C• Having a branch delay slot
- D• All of the above
25Pipe-lining is a unique feature of ___.
- A• RISC
- B• CISC
- C• ISA
- D• IANA
26Performance of a machine is determined by:
- A• Instruction count, Clock cycle time, Clock cycle per instruction
- B• Instruction count, Clock cycle time, Correlating predictors
- C• Clock cycle time, Correlating predictors, Aggressive instruction
- D• Clock cycle time, Clock cycles per instruction, Correlating Predictors
27What do you call the given statement as for type of memory?: “High density, low power, cheap, slow, need to be “refreshed” regularly”
- A• SRAM
- B• DRAM
- C• RAM
28Definition of Block:
- A• minimum unit that is presented or not present
- B• location of block in memory
- C• percentage of item not found in upper level
- D• memory closer to processor
- E• time to access upper level
29Definition of Block address:
- A• minimum unit that is presented or not present
- B• location of block in memory
- C• percentage of item not found in upper level
- D• memory closer to processor
- E• time to access upper level
30 Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[14][14];
int i, j;
for (i = 0; i < 14; i++) {
for (j = 0; j < 14; j++) {
square[i][j].c = 0;
square[i][j].m = 0;
square[i][j].y = 1;
square[i][j].k = 0;
}
}
What is the total number of writes?- A• 784
- B• 512
- C• 1024
31Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[14][14];
int i, j;
for (i = 0; i < 14; i++) {
for (j = 0; j < 14; j++) {
square[i][j].c = 0;
square[i][j].m = 0;
square[i][j].y = 1;
square[i][j].k = 0;
}
}
What is the total number of writes that miss in the cache?- A• 124
- B• 25%
- C• 12.5%
- D• 98
32Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[14][14];
int i, j;
for (i = 0; i < 14; i++) {
for (j = 0; j < 14; j++) {
square[i][j].c = 0;
square[i][j].m = 0;
square[i][j].y = 1;
square[i][j].k = 0;
}
}
What is the miss rate?- A• 98
- B• 25%
- C• 12,5%
- D• 128
33 Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[14][14];
int i, j;
for (i = 0; i < 14; i++) {
for (j = 0; j < 14; j++) {
square[i][j].c = 0;
square[i][j].m = 0;
square[i][j].y = 1;
square[i][j].k = 0;
}
}
What is the hit rate?- A• 896
- B• 686
- C• 12.5%
- D• 87,5%
34Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[14][14];
int i, j;
for (i = 0; i < 14; i++) {
for (j = 0; j < 14; j++) {
square[i][j].c = 0;
square[i][j].m = 0;
square[i][j].y = 1;
square[i][j].k = 0;
}
}
What is the total number of writes that hit in the cache?- A• 686
- B• 784
- C• 12.5%
- D• 87.5%
35. Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[8][8];
int i, j;
for (i = 0; i < 8; i++) {
for (j = 0; j < 8; j++) {
square[i][j].c = 0;
square[i][j].m = 0;
square[i][j].y = 1;
square[i][j].k = 0;
}
}
What is the total number of writes?- A• 256
- B• 1024
- C• 512
- D• 2048
36Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[8][8];
int i, j;
for (i = 0; i < 8; i++) {
for (j = 0; j < 8; j++) {
square[i][j].c = 0;
square[i][j].m = 0;
square[i][j].y = 1;
square[i][j].k = 0;
}
}
What is the total number of writes that miss in the cache?- A• 32
- B• 25%
- C• 12.5%
- D• 128
37. Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[8][8];
int i, j;
for (i = 0; i < 8; i++) {
for (j = 0; j < 8; j++) {
square[i][j].c = 0;
square[i][j].m = 0;
square[i][j].y = 1;
square[i][j].k = 0;
}
}
What is the miss rate?- A• 32
- B• 25%
- C• 12,5%
- D• 128
38Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[8][8];
int i, j;
for (i = 0; i < 8; i++) {
for (j = 0; j < 8; j++) {
square[i][j].c = 0;
square[i][j].m = 0;
square[i][j].y = 1;
square[i][j].k = 0;
}
}
What is the hit rate?- A224
- B32
- C12,5%
- D87,5%
39Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[8][8];
int i, j;
for (i = 0; i < 8; i++) {
for (j = 0; j < 8; j++) {
square[i][j].c = 0;
square[i][j].m = 0;
square[i][j].y = 1;
square[i][j].k = 0;
}
}
What is the total number of writes that hit in the cache?- A224
- B112
- C256
- D524
- E15%
40Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[12][12];
int i, j;
for (i = 0; i < 12; i++) {
for (j = 0; j < 12; j++) {
square[i][j].y = 1;
}
}
for (i = 0; i < 12; i++) {
for (j = 0; j < 12; j++) {
square[i][j].c = 0;
square[i][j].m = 0;
square[i][j].k = 0;
}
}
What is the total number of writes?- A576
- B224
- C112
- D25%
- E12,5%
41Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[12][12];
int i, j;
for (i = 0; i < 12; i++) {
for (j = 0; j < 12; j++) {
square[i][j].y = 1;
}
}
for (i = 0; i < 12; i++) {
for (j = 0; j < 12; j++) {
square[i][j].c = 0;
square[i][j].m = 0;
square[i][j].k = 0;
}
}
What is the total number of writes that miss in the cache?- A256
- B144
- C12,5%
- D25%
- E244
42Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[12][12];
int i, j;
for (i = 0; i < 12; i++) {
for (j = 0; j < 12; j++) {
square[i][j].y = 1;
}
}
for (i = 0; i < 12; i++) {
for (j = 0; j < 12; j++) {
square[i][j].c = 0;
square[i][j].m = 0;
square[i][j].k = 0;
}
}
What is the miss rate?- A25%
- B12,5%
- C144
- D256
- E512
43Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[12][12];
int i, j;
for (i = 0; i < 12; i++) {
for (j = 0; j < 12; j++) {
square[i][j].y = 1;
}
}
for (i = 0; i < 12; i++) {
for (j = 0; j < 12; j++) {
square[i][j].c = 0;
square[i][j].m = 0;
square[i][j].k = 0;
}
}
What is the hit rate?- A144
- B32
- C12,5%
- D75%
44Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[12][12];
int i, j;
for (i = 0; i < 12; i++) {
for (j = 0; j < 12; j++) {
square[i][j].y = 1;
}
}
for (i = 0; i < 12; i++) {
for (j = 0; j < 12; j++) {
square[i][j].c = 0;
square[i][j].m = 0;
square[i][j].k = 0;
}
}
What is the total number of writes that hit in the cache?- A• 432
- B• 87.5%
- C• 75%
- D• 144
45Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[6][6];
int i, j;
for (i = 0; i < 6; i++) {
for (j = 0; j < 6; j++) {
square[i][j].y = 1;
}
}
for (i = 0; i < 6; i++) {
for (j = 0; j < 6; j++) {
square[i][j].c = 0;
square[i][j].m = 0;
square[i][j].k = 0;
}
}
What is the total number of writes?- A576
- B1024
- C36
- D144
46Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[6][6];
int i, j;
for (i = 0; i < 6; i++) {
for (j = 0; j < 6; j++) {
square[i][j].y = 1;
}
}
for (i = 0; i < 6; i++) {
for (j = 0; j < 6; j++) {
square[i][j].c = 0;
square[i][j].m = 0;
square[i][j].k = 0;
}
}
What is the total number of writes that miss in the cache?- A144
- B25%
- C12,5%
- D36
47Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[6][6];
int i, j;
for (i = 0; i < 6; i++) {
for (j = 0; j < 6; j++) {
square[i][j].y = 1;
}
}
for (i = 0; i < 6; i++) {
for (j = 0; j < 6; j++) {
square[i][j].c = 0;
square[i][j].m = 0;
square[i][j].k = 0;
}
}
What is the miss rate?- A36
- B25%
- C12,5%
- D144
48Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[6][6];
int i, j;
for (i = 0; i < 6; i++) {
for (j = 0; j < 6; j++) {
square[i][j].y = 1;
}
}
for (i = 0; i < 6; i++) {
for (j = 0; j < 6; j++) {
square[i][j].c = 0;
square[i][j].m = 0;
square[i][j].k = 0;
}
}
What is the hit rate?- A108
- B32
- C25%
- D75%
49Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[6][6];
int i, j;
for (i = 0; i < 6; i++) {
for (j = 0; j < 6; j++) {
square[i][j].y = 1;
}
}
for (i = 0; i < 6; i++) {
for (j = 0; j < 6; j++) {
square[i][j].c = 0;
square[i][j].m = 0;
square[i][j].k = 0;
}
}
What is the total number of writes that hit in the cache?- A108
- B75%
- C25%
- D12,5%
50Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[14][14];
int i, j;
for (i = 0; i < 14; i++) {
for (j = 0; j < 14; j++) {
square[j][i].c = 0;
square[j][i].m = 0;
square[j][i].y = 1;
square[j][i].k = 0;
}
}
What is the total number of writes?- A196
- B784
- C512
- D1024
51Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[14][14];
int i, j;
for (i = 0; i < 14; i++) {
for (j = 0; j < 14; j++) {
square[j][i].c = 0;
square[j][i].m = 0;
square[j][i].y = 1;
square[j][i].k = 0;
}
}
What is the total number of writes that miss in the cache?- A196
- B512
- C1024
- D784
52Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[14][14];
int i, j;
for (i = 0; i < 14; i++) {
for (j = 0; j < 14; j++) {
square[j][i].c = 0;
square[j][i].m = 0;
square[j][i].y = 1;
square[j][i].k = 0;
}
}
What is the miss rate?- A588
- B25%
- C12,5%
- D288
53Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[14][14];
int i, j;
for (i = 0; i < 14; i++) {
for (j = 0; j < 14; j++) {
square[j][i].c = 0;
square[j][i].m = 0;
square[j][i].y = 1;
square[j][i].k = 0;
}
}
What is the hit rate?- A0,75
- B1
- C0,25
- D0,5
54Following algorithms on a machine with a 2048-byte direct-mapped data cache with 32-byte blocks. You are given the following definitions:
struct point_color {
int c,m,y,k; }
struct point_color square[14][14];
int i, j;
for (i = 0; i < 14; i++) {
for (j = 0; j < 14; j++) {
square[j][i].c = 0;
square[j][i].m = 0;
square[j][i].y = 1;
square[j][i].k = 0;
}
}
for (i = 0; i < 14; i++) {
for (j = 0; j < 14; j++) {
square[j][i].c = 0;
square[j][i].m = 0;
square[j][i].y = 1;
square[j][i].k = 0;
}
}
What is the total number of writes that hit in the cache?- A588
- B784
- C12,5%
- D0,25%
55Choose the right formula of AMAT(апелляционный вопрос!!!)
- A• Average Memory Access time = Hit Time + Miss Rate * Miss penalty
- B• Average Memory Access time = Hit Rate + Miss Rate * Miss penalty
- C• Average Memory Access time = Hit Time + Miss time * Miss penalty
- D• Average Memory Access time = Hit Rate + Miss time * Miss penalty
56What is a RISC computers?
- A• Rational Interruptible Security Computer
- B• Research Interconnect Several Computer
- C• Reduced Instruction Set Computer
57When single-processor performance improvement has dropped?
- A2003
- B2002
- C2004
- D2001
58How much in percentage single-processor performance improvement has dropped to less than?
- A44%
- B33%
- C22%
- D11%
59What is the RLP?
- A• Research Level Parallelism
- B• Request Level Parallelism
- C• Random Level Parallelism
60How many classes of computers classified?
- A7
- B3
- C5
- D1
61Which distance of price has Clusters/warehouse-scale computers?
- A• 100 – 100.000$
- B• 100.000 – 200.000.000$
- C• 5.000 – 10.000.000$
62What is the PMD in computer classes?
- A• Percentage map device
- B• Personal mobile device
- C• Peak maze development
- D• Powerful markup distance
63The Application of Brokerage operations how many cost of downtime per hour?
- A• 8.870.000$
- B• 7.550.000$
- C• 6.450.000$
64What is the Vector Architectures and Graphic Processor Units (GPUs)
- A• Exploits data-level parallelism at modest levels with computer help using ideas like pipelining and at medium levels using ideas like speculative execution
- B• Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
- C• Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
65What is the Thread Level Parallelism
- A• Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads
- B• Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
- C• Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
66What is the Request Level Parallelism
- A• Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
- B• Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads
- C• Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
67What is the Instruction Level Parallelism
- A• Exploits data-level parallelism at modest levels with computer help using ideas like pipelining and at medium levels using ideas like speculative execution
- B• Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
- C• Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
68What is the MISD one of the categories of computers?
- A• Multiple Instruction Streams, Multiple Data Streams
- B• Multiple Instruction Streams, Set Data Stream
- C• Multiple Instructions Streams, Single Data Stream
69How many elements of the Instruction Set Architecture (ISA)
- A8
- B7
- C6
- D5
70How many issue queue used in Centralized Superscalar 2 and Exceptions
- A1
- B2
- C3
- D4
71How many issue queue used in Distributed Superscalar 2 and Exceptions
- A1
- B2
- C3
- D4
72How many instructions used in Distributed Superscalar 2 and Exceptions
- A1
- B2
- C3
- D4
73Which of the following formula is true about Issue Queue for “Instruction Ready”:
- A• Instruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no structural hazards
- B• Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc1)&& no structural hazards
- C• Instruction Ready = (!Vsrc0 || !Psrc1)&&(!Vsrc1 || !Psrc0)&& no structural hazards
- D• Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc0)&& no structural hazards
74What is a ARF?
- A• Architectural Register File
- B• Architecture Relocation File
- C• Architecture Reload File
- D• Architectural Read File
75What is a ROB?
- A• Reorder Buffer
- B• Read Only Buffer
- C• Reload Buffer
- D• Recall Buffer
76What is a FSB?
- A• Finished Store Buffer
- B• Finished Stack Buffer
- C• Finished Stall Buffer
- D• Finished Star Buffer
77What is a PRF?
- A• Physical Register File
- B• Pending Register File
- C• Pipeline Register File
- D• Pure Register File
78What is a SB?
- A• Scoreboard
- B• Scorebased
- C• Scaleboard
- D• Scalebit
79How many stages used in Superscalar (Pipeline)?
- A6
- B3
- C4
- D5
80What is about Superscalar means “F-D-X-M-W”?
- A• Fetch, Decode, Execute, Memory, Writeback
- B• Fetch, Decode, Instruct, Map, Write
- C• Fetch, Decode, Excite, Memory, Write
- D• Fetch, Decode, Except, Map, Writeback
81Speculating on Exceptions “Prediction mechanism” is
- A• Exceptions are rare, so simply predicting no exceptions is very accurate
- B• Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
- C• Only write architectural state at commit point, so can throw away partially executed instructions after exception
- D• None of them
82Speculating on Exceptions “Check prediction mechanism” is
- A• Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
- B• Exceptions are rare, so simply predicting no exceptions is very accurate
- C• The way in which an object is accessed by a subject
- D• None of them
83What is a RT?
- A• Rename Table
- B• Recall Table
- C• Relocate Table
- D• Remove Table
84What is a FL?
- A• Free List
- B• Free Last
- C• Free Leg
- D• Free Launch
85What is an IQ?
- A• Issue Queue
- B• Internal Queue
- C• Interrupt Queue
- D• Instruction Queue
86At VLIW “Superscalar Control Logic Scaling” which parameters are used?
- A• Width and Lifetime
- B• Width and Height
- C• Time and Cycle
- D• Length and Addition
87Out-of-Order Control Complexity MIPS R10000 which element is in Control Logic?
- A• Register name
- B• Instruction cache
- C• Data tags
- D• Data cache
88What is “VLIW”?
- A• Very Long Instruction Word
- B• Very Less Interpreter Word
- C• Very Light Internal Word
- D• Very Low Invalid Word
89At VLIW by “performance and loop iteration” which time is longer?
- A• Loop Unrolled
- B• Software Pipelined
90At VLIW by “performance and loop iteration” which time is shorter?
- A• Software Pipelined
- B• Loop Unrolled
91At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion?
- A• Speculative operations that don’t cause exceptions
- B• Hardware to check pointer hazards
92At VLIW by “performance and loop iteration” which time is shorter?
- A• Software Pipelined
- B• Loop Unrolled
93At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion?
- A• Speculative operations that don’t cause exceptions
- B• Hardware to check pointer hazards
94At VLIW Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
- A• Hardware to check pointer hazards
- B• Speculative operations that don’t cause exceptions
95What is an ALAT?
- A• Advanced Load Address Table
- B• Allocated Link Address Table
- C• Allowing List Address Table
- D• Addition Long Accessibility Table
96What is a Compulsory?
- A• first-reference to a block, occur even with infinite cache
- B• cache is too small to hold all data needed by program, occur even under perfect replacement policy
- C• misses that occur because of collisions due to less than full associativity
97What is a Capacity?
- A• cache is too small to hold all data needed by program, occur even under perfect replacement policy
- B• first-reference to a block, occur even with infinite cache
- C• misses that occur because of collisions due to less than full associativity
98The computer architecture having stored program is ___.
- A• Harvard
- B• Von Neumann
- C• Pascal
- D• Ada
- E• Cobol
99The key technology used in IV generation computers is ___.
- A• MSI
- B• SSI
- C• LSI & VLSI
- D• Transistors
- E• Vacuum Tubes
100The digital circuit that generates the arithmetic sum of two binary numbers of any length is ___.
- A• Binary Adder
- B• Full Adder
- C• Half Adder
- D• Adder
- E• OR gate
101Which one of the following is a memory whose duty is to store most frequently used data?
- A• Main memory
- B• Cache
- C• ROM
- D• Auxiliary memory
- E• PROM
102 How many bytes equals Petabyte (PB)?
- A• Quadrillion
- B• Million
- C• Trillion
- D• Billion
- E• 1000
Information
- Description
- Quiz on Untitled, created by Nassiba Zainullayeva on 18/12/2018.
- Author
- Nassiba Zainullayeva
- Language
- English
- Views
- 0
- Rating
- No ratings yet Rate this quiz