Quiz
PC
Erstelle ein kostenloses Konto, um dieses Quiz zu beenden
Speichere deinen Fortschritt und sieh dir dein Endergebnis an.
oder mit deiner E-Mail registrieren
Schon ein Konto? Anmelden
Fragen in diesem Quiz (191)
1At VLIW Speculative Execution, which of this solution is true about problem:
Branches restrict compiler code motion?- ASpeculative operations that don’t cause exceptions
- BHardware to check pointer hazards
2At VLIW Speculative Execution, which of this solution is true about problem:
Possible memory hazards limit code scheduling:- AHardware to check pointer hazards
- BSpeculative operations that don’t cause exceptions
3What is an ALAT?
- AAdvanced Load Address Table
- BAllocated Link Address Table
- CAllowing List Address Table
- DAddition Long Accessibility Table
4At VLIW Multi-Way Branches, which of this solution is true about problem: Long
instructions provide few opportunities for branches:- AAllow one instruction to branch multiple directions
- BSpeculative operations that don’t cause exceptions
5What is a Latency:
- Ais time for a single access – Main memory latency is usually >> than processor cycle time
- Bis the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses
per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle - Cis amount of data that can be in flight at the same time (Little’s Law)
6What is a Compulsory?
- Afirst-reference to a block, occur even with infinite cache
- Bcache is too small to hold all data needed by program, occur even under perfect replacement policy
- Cmisses that occur because of collisions due to less than full associativity
7What is a Capacity?
- Acache is too small to hold all data needed by program, occur even under perfect replacement policy
- Bfirst-reference to a block, occur even with infinite cache
- Cmisses that occur because of collisions due to less than full associativity
8What occurs at Intruction fetches when we speak about Common And Predictable Memory
Reference Patterns?- An loop iterations
- Bsubroutine call
- Cvector access
9What is a Conflict?
- Amisses that occur because of collisions due to less than full associativity
- Bfirst-reference to a block, occur even with infinite cache
- Ccache is too small to hold all data needed by program, occur even under perfect replacement policy
10What occurs at Stack access when we speak about Common And Predictable Memory
Reference Patterns?- Asubroutine call
- Bn loop iterations
- Cvector access
11In Multilevel Caches “Local miss rate” equals =
- Amisses in cache / accesses to cache
- Bmisses in cache / CPU memory accesses
- Cmisses in cache / number of instructions
12What occurs at Data access when we speak about Common And Predictable Memory
Reference Patterns?- Asubroutine call
- Bn loop iterations
- Cvector access
13In Multilevel Caches “Global miss rate” equals =
- Amisses in cache / CPU memory accesses
- Bmisses in cache / accesses to cache
- Cmisses in cache / number of instructions
14In Multilevel Caches “Misses per instruction” equals =
- Amisses in cache / number of instructions
- Bmisses in cache / accesses to cache
- Cmisses in cache / CPU memory accesses
15Cache HIT:
- ANo Write Allocate, Write Allocate
- BWrite Through, Write Back
16Non-Blocking Cache Timeline for “Blocking Cache” the sequence is - ?
- ACPU time-Cache Miss-Miss Penalty-CPU time
- BCPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
- CCPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time
17Non-Blocking Cache Timeline for “Hit Under Miss” the sequence is -?
- ACPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
- BCPU time-Cache Miss-Miss Penalty-CPU time
- CCPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time
18Non-Blocking Cache Timeline for “Miss Under Miss” the sequence is -?
- ACPU time->Cache Miss->Miss->Stall on use->Miss Penalty->Miss Penalty->CPU time
- BCPU time-Cache Miss-Miss Penalty-CPU time
- CCPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
19What does mean MSHR?
- AMiss Status Handling Register
- BMap Status Handling Reload
- CMips Status Hardware Register
- DMemory Status Handling Register
20What does MAF?
- AMiss Address File
- BMap Address File
- CMemory Address File
21At Critical Word First for Miss Penalty chose correct sequence of Basic Blocking
Cache “Order of fill”:- A0,1,2,3,4,5,6,7
- B3,4,5,6,7,0,1,2
22At Critical Word First for Miss Penalty chose correct sequence of Blocking
Cache with Critical Word first “Order of fill”:- A3,4,5,6,7,0,1,2
- B0,1,2,3,4,5,6,7
23Storage Systems, “Larger block size to reduce miss rate” -
- AThe simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size
- BThe obvious way to reduce capacity misses is to increase cache capacity
- CObviously, increasing associativity reduces conflict misses
24Storage Systems, “Bigger caches to reduce miss rate” -
- AThe obvious way to reduce capacity misses is to increase cache capacity
- BObviously, increasing associativity reduces conflict misses
- CThe simplest way to reduce the miss rate is to take advantage of spatial locality and increase
the block size
25Storage Systems, “Higher associativity to reduce miss rate” -
- AObviously, increasing associativity reduces conflict misses
- BThe obvious way to reduce capacity misses is to increase cache capacity
- CThe simplest way to reduce the miss rate is to take advantage of spatial locality and increase
the block size
26In Non-Blocking Caches what does mean “Critical Word First”?
- ARequest the missed word first from memory and send it to the processor as soon as it arrives;
let the processor continue execution while filling the rest of the words in the block - BFetch the words in normal order, but as soon as the requested word of the block arrives,
send it to the processor and let the processor continue execution
- ARequest the missed word first from memory and send it to the processor as soon as it arrives;
27In Non-Blocking Caches what does mean “Early restart”?
- AFetch the words in normal order, but as soon as the requested word of the block arrives, send
it to the processor and let the processor continue execution - BRequest the missed word first from memory and send it to the processor as soon as it
arrives; let the processor continue execution while filling the rest of the words in the block
- AFetch the words in normal order, but as soon as the requested word of the block arrives, send
28A virus classification by target includes the following categories, What is a File
infector?- AInfects files that the operating system or shell consider to be executable
- BA typical approach is as follows
- CThe key is stored with the virus
- DFar more sophisticated techniques are possible
29What is a RAID 0?
- AIt has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although
the data may be striped across the disks in the array - BAlso called mirroring or shadowing, there are two copies of every piece of data
- CThis organization was inspired by applying memory-style error correcting codes to disks
- AIt has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although
30What is a RAID 1?
- AAlso called mirroring or shadowing, there are two copies of every piece of data
- BIt has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,”
although the data may be striped across the disks in the array - CThis organization was inspired by applying memory-style error correcting codes to disks
31What is a RAID 2?
- AThis organization was inspired by applying memory-style error correcting codes to disks
- BIt has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,”
although the data may be striped across the disks in the array - CAlso called mirroring or shadowing, there are two copies of every piece of data
32What is a RAID 3?
- ASince the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed
- BMany applications are dominated by small accesses
- CAlso called mirroring or shadowing, there are two copies of every piece of data
33What is a RAID 4?
- AMany applications are dominated by small accesses
- BSince the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk
failed - CAlso called mirroring or shadowing, there are two copies of every piece of data
34At storage systems Gray and Siewiorek classify faults what does mean
“Hardware faults”? :- ADevices that fail, such as perhaps due to an alpha particle hitting a memory cell
- BFaults in software (usually) and hardware design (occasionally)
- CMistakes by operations and maintenance personnel
35At storage systems Gray and Siewiorek classify faults what does mean “Design
faults”? :- AFaults in software (usually) and hardware design (occasionally)
- BDevices that fail, such as perhaps due to an alpha particle hitting a memory cell
- CMistakes by operations and maintenance personnel
36At storage systems Gray and Siewiorek classify faults what does mean
“Operation faults”? :- AMistakes by operations and maintenance personnel
- BDevices that fail, such as perhaps due to an alpha particle hitting a memory cell
- CFaults in software (usually) and hardware design (occasionally)
37At storage systems Gray and Siewiorek classify faults what does mean
“Environmental faults”? :- AFire, flood, earthquake, power failure, and sabotage
- BFaults in software (usually) and hardware design (occasionally)
- CDevices that fail, such as perhaps due to an alpha particle hitting a memory cell
38If we talk about storage systems an interaction or transaction with a computer is
divided for first what is an “Entry time” - ? :- AThe time for the user to enter the command
- BThe time between when the user enters the command and the complete response is displayed
- CThe time from the reception of the response until the user begins to enter the next command
39If we talk about storage systems an interaction or transaction with a
computer is divided for first what is an “System response time” - ?:- AThe time between when the user enters the command and the complete response is displayed
- BThe time for the user to enter the command
- CThe time from the reception of the response until the user begins to enter the next command
40If we talk about storage systems an interaction or transaction with a
computer is divided for first what is an “Think time” - ?:- AThe time from the reception of the response until the user begins to enter the next command
- BThe time for the user to enter the command
- CThe time between when the user enters the command and the complete response is displayed
41Little’s Law and a series of definitions lead to several useful equations for
“Time server” - :- AAverage time to service a task; average service rate is 1/Time server traditionally represented
by the symbol µ in many queuing texts - BAverage time per task in the queue
- CAverage time/task in the system, or the response time, which is the sum of Time queue and Time server
- AAverage time to service a task; average service rate is 1/Time server traditionally represented
42Little’s Law and a series of definitions lead to several useful equations for
“Time queue” - :- AAverage time per task in the queue
- BAverage time to service a task; average service rate is 1/Time server traditionally
represented by the symbol µ in many queuing texts - CAverage time/task in the system, or the response time, which is the sum of Time queue and Time server
43Little’s Law and a series of definitions lead to several useful equations for
“Time system” - :- AAverage time/task in the system, or the response time, which is the sum of Time queue and Time server
- BAverage time to service a task; average service rate is 1/Time server traditionally
represented by the symbol µ in many queuing texts - CAverage time per task in the queue
44Little’s Law and a series of definitions lead to several useful equations for
“Length server” - :- AAverage number of tasks in service
- BAverage length of queue
45Little’s Law and a series of definitions lead to several useful equations for
“Length queue” -:- AAverage length of queue
- BAverage number of tasks in service
46How many size of Cache L1 is true approximately? :
- A8 KB
- B256 KB
- C2 MB
47How many size of Cache L2 is true approximately? :
- A256 KB
- B4 KB
- C32 MB
48How many size of Cache L3 is true approximately? :
- A3 MB
- B256 MB
- C256 KB
49How many main levels of Cache Memory?
- A3
- B2
- C6
- D8
50What is a “Synchronization” in Cache Memory?
- AExecution in the OS that is neither idle nor in synchronization access
- BExecution in user code
- CExecution or waiting for synchronization variables
51What is a “Kernel” in Cache Memory?
- AExecution or waiting for synchronization variables
- BExecution in the OS that is neither idle nor in synchronization access
- CExecution in user code
52What is a “Synchronization” in Cache Memory?
- AExecution in the OS that is neither idle nor in synchronization access
- BExecution in user code
- CExecution or waiting for synchronization variables
53What is a “Kernel” in Cache Memory?
- AExecution or waiting for synchronization variables
- BExecution in the OS that is neither idle nor in synchronization access
- CExecution in user code
54What is a “Synchronization” in Cache Memory?
- AExecution in the OS that is neither idle nor in synchronization access
- BExecution in user code
- CExecution or waiting for synchronization variables
55What is a “Kernel” in Cache Memory?
- AExecution or waiting for synchronization variables
- BExecution in the OS that is neither idle nor in synchronization access
- CExecution in user code
56Network performance depends of what?
- Aperformance of swithes and transmission system
- Bperformance of switches
- Cperformance of transmission system
- Dhas no dependensies
57The time between the start and the completion of an event ,such as milliseconds
for a disk access is...- Alatency
- Bbandwidth
- Cthroughput
- Dperformance
58Total amount of work done in a given time ,such as megabytes per second for disk
transfer...- Abandwidth
- Blatency
- Cthroughput
- Dperformance
59Learning curve itself is best measured by change in...
- Ayeld
- Bbytes
- Cbits
- Dseconds
60Cache MISS:
- ANo Write Allocate, Write Allocate
- BWrite Through, Write Back
61Products that are sold by multiple vendors in large volumes and are essentialy
identical- Acommodities
- Bboxes
- Cfolders
- Dfiles
62Average Memory Access Time is equal:
- AHit Time * ( Miss Rate + Miss Penalty )
- BHit Time - ( Miss Rate + Miss Penalty )
- CHit Time / ( Miss Rate - Miss Penalty )
- DHit Time + ( Miss Rate * Miss Penalty )
63Integrated circuit processes are charecterized by the
- Afeature size
- Bpermanent size n
- Ccompex size
- Dfixed size
64Compulsory -
- Acache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache
lines) - Bfirst-reference to a block, occur even with infinite cache
- Cmisses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
- Acache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache
65For CMOS chips, the traditional dominant energy consumption has been in
switching transistors, called ____- Adynamic power
- Bphysical energy
- Cconstant supply
- Dsimple battery
66Manufacturing costs that decrease over time are ____
- Athe learning curve
- Bthe cycled line
- Cthe regular option
- Dthe final loop
67Capacity -
- Acache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache
lines) - Bmisses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
lines) - Cfirst-reference to a block, occur even with infinite cache
- Acache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache
68Volume is a ________ key factor in determining cost.
- Asecond
- Bfirst
- Cfifth
- Dthird
69The most companies spend only ____________ of their income on R&D, which
includes all engineering.- A4% to 12%
- B15% to 30%
- C1% to 17%
- D30% to 48%
70Conflict -
- Afirst-reference to a block, occur even with infinite cache
- Bmisses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
- Ccache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache
lines)
71Systems alternate between two states of service with respect to an SLA:
- A1. Service accomplishment, where the service is delivered as specified
2. Service interruption, where the delivered service is different from the SLA - B1. Service accomplishment, where the service is not delivered as specified
2. Service interruption, where the delivered service is different from the SLA - C1. Service accomplishment, where the service is not delivered as specified
2. Service interruption, where the delivered service is not different from the SLA - D1. Service accomplishment, where the service is delivered as specified
2. Service interruption, where the delivered service is not different from the SLA
- A1. Service accomplishment, where the service is delivered as specified
72Algorithm for Cache HIT:
- AProcessor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from
cache - BProcessor issues load request to cache -> Read block of data from main memory -> return copy of data from cache
- CProcessor issues load request to cache -> Compare request address to cache tags and see if there is a match -> return
copy of data from cache
- AProcessor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from
73Desktop benchmarks divide into __ broad classes:
- Atwo
- Bthree
- Cfour
- Dfive
74Algorithm for Cache MISS:
- AProcessor issues load request to cache -> Compare request address to cache tags and see if there is a match -> Read
block of data from main memory -> Replace victim block in cache with new block -> return copy of data from cache - BProcessor issues load request to cache -> Read block of data from main memory -> return copy of data from cache
- CProcessor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from
cache
- AProcessor issues load request to cache -> Compare request address to cache tags and see if there is a match -> Read
75What MTTF means:
- Amean time to failure
- Bmean time to feauture
- Cmean this to failure
- Dmy transfers to failure
76The formula of “Iron Law” of Processor Performance:
- Atime/program = instruction/program * cycles/instruction * time/cycle
- Btime/program = instruction/program * cycles/instruction + time/cycle
- Ctime/program = instruction/program + cycles/instruction * time/cycle
77A widely held rule of thumb is that a program spends __ of its execution time in
only __ of the code.- A90% 10%
- B50% 50%
- C70% 30%
- D89% 11%
78Structural Hazard:
- AAn instruction in the pipeline needs a resource being used by another instruction in the pipeline
- BAn instruction depends on a data value produced by an earlier instruction
- CWhether or not an instruction should be executed depends on a control decision made by an earlier instruction
79(Performance for entire task using the enhancement when possible) / (Performance for entire task without using the enhancement) is equals to:
- ASpeedup
- BEfficiency
- CProbability
- DRation
80Which of the following descriptions corresponds to static power?
- AGrows proportionally to the transistor count (whether or not the transistors are switching)
- BProportional to the product of the number of switching transistors and the switching rate
Probability - CProportional to the product of the number of switching transistors and the switching rate
- DAll of the above
81Which of the following descriptions corresponds to dynamic power?
- AProportional to the product of the number of switching transistors and the switching rate
- BGrows proportionally to the transistor count (whether or not the transistors are switching)
- CCertainly a design concern
- DNone of the above
82Data Hazard:
- AAn instruction depends on a data value produced by an earlier instruction
- BAn instruction in the pipeline needs a resource being used by another instruction in the pipeline
- CWhether or not an instruction should be executed depends on a control decision made by an earlier instruction
83Control Hazard:
- AWhether or not an instruction should be executed depends on a control decision made by an earlier instruction
- BAn instruction depends on a data value produced by an earlier instruction
- CAn instruction in the pipeline needs a resource being used by another instruction in the pipeline
84What is a Bandwidth:
- Aa is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI
= 1 requires at least 1 + m memory accesses per cycle - Bis time for a single access – Main memory latency is usually >> than processor cycle time
- Cis amount of data that can be in flight at the same time (Little’s Law)
- Aa is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI
85What is a Bandwidth-Delay Product:
- Ais amount of data that can be in flight at the same time (Little’s Law)
- Bis time for a single access – Main memory latency is usually >> than processor cycle time
- Cis the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI
= 1 requires at least 1 + m memory accesses per cycle
86What is Computer Architecture?
- Ais the design of the abstraction/implementation layers that allow us to execute information processing applications
efficiently using manufacturing technologies - Bis a group of computer systems and other computing hardware devices that are linked together through communication
channels to facilitate communication and resource-sharing among a wide range of users - Cthe programs used to direct the operation of a computer, as well as documentation giving instructions on how to use
them
- Ais the design of the abstraction/implementation layers that allow us to execute information processing applications
87Least Recently Used (LRU):
- Acache state must be updated on every access
- BUsed in highly associative caches
- CFIFO with exception for most recently used block(s)
88Cache Hit -
- AWrite Through – write both cache and memory, generally higher traffic but simpler to design
- Bwrite cache only, memory is written when evicted, dirty bit per block avoids unnecessary write backs, more complicated
- CNo Write Allocate – only write to main memory
89Reduce Miss Rate: Large Cache Size. Empirical Rule of Thumb:
- AIf cache size is doubled, miss rate usually drops by about √2
- BDirect-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
- CNone of them
90Reduce Miss Rate: High Associativity. Empirical Rule of Thumb:
- ADirect-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
- BIf cache size is doubled, miss rate usually drops by about √2
- CNone of them
91Exploit temporal locality:
- Aby remembering the contents of recently accessed locations
- Bby fetching blocks of data around recently accessed locations
- CNone of them
92Exploit spatial locality:
- Aby remembering the contents of recently accessed locations
- Bby fetching blocks of data around recently accessed locations
- CNone of them
93Exploit spatial locality:
- Aby fetching blocks of data around recently accessed locations
- Bby remembering the contents of recently accessed locations
- CNone of them
94What is the access time?
- ATime between when a read is requested and when the desired word arrives
- BThe minimum time between requests to memory.
- CDescribes the technology inside the memory chips and those innovative, internal organizations
- DNone of them
95What is the cycle time?
- AThe minimum time between requests to memory.
- BTime between when a read is requested and when the desired word arrives
- CThe maximum time between requests to memory.
- DNone of them
96What does SRAM stands for?
- AStatic Random Access memory
- BSystem Random Access memory
- CShort Random Accessmemory
- DNone of them
97What does DRAM stands for?
- ADynamic Random Access memory
- BDual Random Access memory
- CDataram Random Access memory
98What does DDR stands for?
- ADouble data rate
- BDual data rate
- CDouble data reaction
- DNone of them
99What is kernel process?
- AProvide at least two modes, indicating whether the running process is a user process or an
operating system process - BProvide at least five modes, indicating whether the running process is a user process or an
operating system process - CProvide a portion of the processor state that a user process can use but not write
- DNone of them
- AProvide at least two modes, indicating whether the running process is a user process or an
100Which one is NOT concerning to pitfall?
- APredicting cache performance of one program from another
- BSimulating enough instructions to get accurate performance measures of the memory hierarchy
- CImplementing a virtual machine monitor on an instruction set architecture that wasn’t designed to
be virtualizable - DOver emphasizing memory bandwidth in DRAMs
101Which one is concerning to fallacy?
- APredicting cache performance of one program from another
- BSimulating enough instructions to get accurate performance measures of the memory hierarchy
- CImplementing a virtual machine monitor on an instruction set architecture that wasn’t designed to
be virtualizable - DOver emphasizing memory bandwidth in DRAMs
102If we talk about storage systems an interaction or transaction with a computer is
divided for first what is an “System response time” - ?:- AThe time between when the user enters the command and the complete response is displayed
- BThe time for the user to enter the command
- CThe time from the reception of the response until the user begins to enter the next command
103If we talk about storage systems an interaction or transaction with a computer is
divided for first what is an “Think time” - ?:- AThe time from the reception of the response until the user begins to enter the next command
- BThe time for the user to enter the command
- CThe time between when the user enters the command and the complete response is displayed
104Little’s Law and a series of definitions lead to several useful equations for “Time
server” - :- AAverage time to service a task; average service rate is 1/Time server traditionally represented
by the symbol μ in many queuing texts - BAverage time per task in the queue
- CAverage time/task in the system, or the response time, which is the sum of Time queue and Time server
- AAverage time to service a task; average service rate is 1/Time server traditionally represented
105Little’s Law and a series of definitions lead to several useful equations for “Time
queue” - :- AAverage time per task in the queue
- BAverage time to service a task; average service rate is 1/Time server traditionally
represented by the symbol μ in many queuing texts - CAverage time/task in the system, or the response time, which is the sum of Time queue and Time server
106Little’s Law and a series of definitions lead to several useful equations for “Time
system” - :- AAverage time/task in the system, or the response time, which is the sum of Time queue and Time server
- BAverage time to service a task; average service rate is 1/Time server traditionally
represented by the symbol μ in many queuing texts - CAverage time per task in the queue
107Little’s Law and a series of definitions lead to several useful equations for
“Length server” - :- AAverage number of tasks in service
- BAverage length of queue
108Little’s Law and a series of definitions lead to several useful equations for
“Length queue” -:- AAverage length of queue
- BAverage number of tasks in service
109How many issue queue used in Centralized Superscalar 2 and Exceptions?
- A4
- B3
- C2
- D1
110How many issue queue used in Distributed Superscalar 2 and Exceptions:
- A4
- B3
- C1
- D2
111How many instructions used in Distributed Superscalar 2 and Exceptions?
- A4
- B3
- C2
- D1
112How many issue queue used in Centralized Superscalar 2 and Exceptions?
- A1
- B2
- C3
- D4
113Which of the following formula is true about Issue Queue for “Instruction
Ready”:- AInstruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no structural hazards
- BInstruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc1)&& no structural hazards
- CInstruction Ready = (!Vsrc0 || !Psrc1)&&(!Vsrc1 || !Psrc0)&& no structural hazards
- DInstruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc0)&& no structural hazards
114What is a ARF:
- AArchitectural Register File
- BArchitecture Relocation File
- CArchitecture Reload File
- DArchitectural Read File
115What is a ROB?
- AReorder Buffer
- BRead Only Buffer
- CReload Buffer
- DRecall Buffer
116What is a FSB?
- AFinished Store Buffer
- BFinished Stack Buffer
- CFinished Stall Buffer
- DFinished Star Buffer
117What is a PRF?
- APhysical Register File
- BPending Register File
- CPipeline Register File
- DPure Register File
118What is a SB?
- AScoreboard
- BScorebased
- CScaleboard
- DScalebit
119How many stages used in Superscalar (Pipeline)?
- A5
- B4
- C6
- D7
120What is about Superscalar means “F-D-X-M-W”?
- AFetch, Decode, Execute, Memory, Writeback
- BFetch, Decode, Instruct, Map, Write
- CFetch, Decode, Excite, Memory, Write
- DFetch, Decode, Except, Map, Writeback
121Speculating on Exceptions “Prediction mechanism” is -
- AExceptions are rare, so simply predicting no exceptions is very accurate
- BExceptions detected at end of instruction execution pipeline, special hardware for various exception types
- COnly write architectural state at commit point, so can throw away partially executed instructions after
exception - DNone of them
122Speculating on Exceptions “Check prediction mechanism” is -
- AExceptions detected at end of instruction execution pipeline, special hardware for various exception types
- BExceptions are rare, so simply predicting no exceptions is very accurate
- CThe way in which an object is accessed by a subject
- DNone of them
123Speculating on Exceptions “Recovery mechanism” is -
- AOnly write architectural state at commit point, so can throw away partially executed instructions after
exception - BExceptions are rare, so simply predicting no exceptions is very accurate
- CAn entity capable of accessing objects
- DNone of them
- AOnly write architectural state at commit point, so can throw away partially executed instructions after
124What is a RT?
- ARename Table
- BRecall Table
- CRelocate Table
- DRemove Table
125What is a FL?
- AFree List
- BFree Last
- CFree Leg
- DFree Launch
126What is an IQ?
- AIssue Queue
- BInternal Queue
- CInterrupt Queue
- DInstruction Queue
127At VLIW “Superscalar Control Logic Scaling” which parameters are used?
- AWidth and Lifetime
- BWidth and Height
- CTime and Cycle
- DLength and Addition
128Out-of-Order Control Complexity MIPS R10000 which element is in Control
Logic?- ARegister name
- BInstruction cache
- CData tags
- DData cache
129Out-of-Order Control Complexity MIPS R10000 which element is not in Control
Logic?- AInteger Datapath
- BCLK
- CFree List
- DAddress Queue
130What is “VLIW”?
- AVery Long Instruction Word
- BVery Less Interpreter Word
- CVery Light Internal Word
- DVery Low Invalid Word
131At VLIW by “performance and loop iteration” which time is longer?
- ALoop Unrolled
- BSoftware Pipelined
132At VLIW by “performance and loop iteration” which time is shorter?
- ASoftware Pipelined
- BLoop Unrolled
133A simple scheme for increasing the number of instructions relative to the branch and
overhead instructions is…?- Aloop unrolling
- BRAR
- Cloop-level
- Dloop rolling
134Effect that results from instruction scheduling in large code segments is called…?
- Aregister pressure
- Bloop unrolling
- Cloop-level
- Dregistration
135The simplest dynamic branch-prediction scheme is a
- Abranch-prediction buffer
- Bbranch buffer
- CAll answers correct
- Dregistration
136Branch predictors that use the behavior of other branches to make a prediction are called
- Acorrelating predictors or two-level predictors
- Bbranch-prediction buffer
- Cbranch table
- Dthree level loop
137How many branch-selected entries are in a (2,2) predictor that has a total of 8K bits in the
prediction buffer? If we know that Number of prediction entries selected by the branch = 8K- Athe number of prediction entries selected by the branch = 1K.
- Bthe number of prediction entries selected by the branch = 2K.
- Cthe number of prediction entries selected by the branch = 8K.
- Dthe number of prediction entries selected by the branch = 4K.
138What is the compulsory in Cs model?
- AThe very first access to a block cannot be in the cache, so the block must be brought into the cache.
Compulsory misses are those that occur even if you had an infinite cache. - BIf the cache cannot contain all the blocks needed during execution of a program, capacity misses
(in addition to compulsory misses) will occur because of blocks being discarded and later
retrieved - CThe number of accesses that miss divided by the number of accesses.
- DNone of them
- AThe very first access to a block cannot be in the cache, so the block must be brought into the cache.
139What is capacityin Cs model?
- AIf the cache cannot contain all the blocks needed during execution of a program, capacity misses
(in addition to compulsory misses) will occur because of blocks being discarded and later retrieved - BThe very first access to a block cannot be in the cache, so the block must be brought into the
cache. Compulsory misses are those that occur even if you had an infinite cache. - CThe number of accesses that miss divided by the number of accesses.
- DNone of them
- AIf the cache cannot contain all the blocks needed during execution of a program, capacity misses
140What is conflict in Cs model?
- AIf the block placement strategy is not fully associative, conflict misses (in addition to compulsory
and capacity misses) will occur because a block may be discarded and later retrieved if conflicting
blocks map to its set - BThe very first access to a block cannot be in the cache, so the block must be brought into the
cache. Compulsory misses are those that occur even if you had an infinite cache. - CIf the cache cannot contain all the blocks needed during execution of a program, capacity misses
(in addition to compulsory misses) will occur because of blocks being discarded and later
retrieved - DNone of them
- AIf the block placement strategy is not fully associative, conflict misses (in addition to compulsory
141Choose the benefit of Cache Optimization.
- ALarger block size to reduce miss rate
- BBigger caches to increase miss rat
- CSingle level caches to reduce miss penalty
- DNone of them
142Choose the strategy of Seventh Optimization.
- ACritical word first
- BCritical restart
- CSequential inter leaving
- DMerging Write Buffer to Reduce Miss Penalty
143ChoosetheEightOptimization
- AMerging Write Buffer to Reduce Miss Penalty
- BCritical word first
- CNonblocking Caches to Increase Cache Bandwidth
- DTrace Caches to Reduce Hit Time
144ChoosetheEleventhOptimization
- ACompiler-Controlled Prefetching to Reduce Miss Penalty or Miss Rate
- BMerging Write Buffer to Reduce Miss Penalty
- CHardware Prefetching of Instructions and Data to Reduce Miss Penalty or Miss Rate
- DNone of them
145What is the access time?
- ATime between when a read is requested and when the desired word arrives
- BThe minimum time between requests to memory.
- CDescribes the technology inside the memory chips and those innovative, internal organizations
- DNone of them
146What is the cycle time?
- AThe minimum time between requests to memory.
- BTime between when a read is requested and when the desired word arrives
- CThe maximum time between requests to memory.
- DNone of them
147What is kernel process?
- AProvide at least two modes, indicating whether the running process is a user process or an
operating system process - BProvide at least five modes, indicating whether the running process is a user process or an
operating system process - CProvide a portion of the processor state that a user process can use but not write
- DNone of them
- AProvide at least two modes, indicating whether the running process is a user process or an
148Which one is NOT concerning to pitfall?
- APredicting cache performance of one program from another
- BSimulating enough instructions to get accurate performance measures of the memory hierarchy
- CImplementing a virtual machine monitor on an instruction set architecture that wasn’t designed to
be virtualizable - DOver emphasizing memory bandwidth in DRAMs
149Which one is concerning to fallacy?
- APredicting cache performance of one program from another
- BSimulating enough instructions to get accurate performance measures of the memory hierarchy
- CImplementing a virtual machine monitor on an instruction set architecture that wasn’t designed to
be virtualizable - DOver emphasizing memory bandwidth in DRAMs
150How much in percentage single-processor performance improvement has dropped to
less than?- A11%
- B22%
- C33%
151Which of the written below is NOT increase power consumption?
- AIncreasing multithreading
- BIncreasing performance
- CIncreasing multiple cores
152How many elements of the Instruction Set Architecture (ISA):
- A6
- B7
- C8
153What is the Thread Level Parallelism –
- AExploit data-level parallelism by applying a single instruction to a collection of data in parallel.
- BExploits parallelism among largely decoupled tasks specified by the programmer or operating system.
- CExploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that
allows for interaction among parallel threads.
154Growing performance gap between peak and sustained performance translates to
increasing energy per unit of performance, when:- AThe number of transistors switching will be proportional to the peak issue rate, and the
performance is proportional to the sustained rate - BThe number of transistors switching will be proportionalto the sustained rate, and the
performance is proportionalto the peak issue rate - CThe number of transistors switching will be proportional to the sustained rate
- DThe performance is proportional to the peak issue rate
- AThe number of transistors switching will be proportional to the peak issue rate, and the
155What is the PMD in computer classes?
- APersonal mobile device
- BPowerful markup distance
- CPercentage map device
156If we want to sustain four instructions per clock
- AWe must fetch more, issue more, and initiate execution on more than four instructions
- BWe must fetch less, issue more, and initiate execution on more than two instructions
- CWe must fetch more, issue less, and initiate execution on more than three instructions
- DWe must fetch more, issue more, and initiate execution on less than five instructions
157What is the RLP?
- ARandom Level Parallelism
- BRequest Level Parallelism
- CResearch Level Parallelism
158If speculation were perfect, it could save power, since it would reduce the execution time and
save _____________, while adding some additional overhead to implement- AStatic power
- BDynamic power
- CProcessing rate
- DProcessor state
159What is the Instruction Level Parallelism:
- AExploit data-level parallelism by applying a single instruction to a collection of data in parallel.
- BExploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at a
medium levels using ideas like speculative execution. - CExploits parallelism among largely decoupled tasks specified by the programmer or operating system.
160When speculation is not perfect, it rapidly becomes energy inefficient, since it requires
additional ___________ both for the incorrect speculation and for the resetting of the processor
state- ADynamic power
- BStatic power
- CProcessing rate
- DProcessor state
161Which distance of price has Cluster/warehouse-scale computers?
- A5 000 – 10 000 000 $
- B100 000 – 200 000 000 $
- C100 – 100 000 $
162Which of these concepts is NOT illustrated case study by Wen-mei W. Hwu and John W.
Sias- AAchievable ILP with software resource constraints
- BLimited ILP due to software dependences
- CAchievable ILP with hardware resource constraints
- DVariability of ILP due to software and hardware interaction
163The Application of Brokerage operations how many cost of downtime per hour?
- A8 870 000 $
- B7 550 000 $
- C6 450 000 $
164What is a hash table?
- APopular data structure for organizing a large collection of data items so that one can quickly answer questions
- BPopular data structure for updating large collections, so that one can hardly answer questions
- CPopular tables for organizing a large collection of data structure
- DPopular data structure for deletingsmall collections of data items so that one can hardly
answer questions
165How many elements in Trends of Technology?
- A5
- B6
- C4
166Which of these is NOT characteristics of recent highperformance microprocessors?
- AColor
- BPower
- CFunctional unit capability
- DClock rate
167How this process called: “Operations execute as soon as their operands are available”
- Adata flow execution
- Binstruction execution
- Cdata control execution
- Dinstruction field execution
168For what the reorder buffer is used :
- ATo pass results among instructions that may be speculated.
- BTo pass parameters through instructions that may be speculated
- CTo get additional registers in the same way as the reservation stations
- DTo control registers
169How many fields contains the entry in the ROB:
- A4
- B5
- C6
- D3
170Choose correct fields of entry in the ROB:
- Athe instruction type, the destination field, the value field, and the ready field
- Bthe source type, the destination field, the value field, and the ready field
- Cthe program type, the ready field, the parameter field, the destination field
- Dthe instruction type, the destination field, and the ready field
171Choose the steps of instruction execution:
- Aissue, execute, write result, commit
- Bexecution, commit, rollback
- Cissue, execute, override, exit
- Dbegin, write, interrupt, commit
172Which one is not the major flavor of Multiple-issue processors:
- Astatistically superscalar processors
- Bdynamically scheduled superscalar processors
- Cstatically scheduled superscalar processors
- DVLIW (very long instruction word) processors
173Which Multiple-issue processors has not the hardware hazard detection:
- AEPIC
- BSuperscalar(dynamic)
- CSuperscalar(static)
- DSuperscalar(speculative)
174Examples of EPIC:
- AItanium
- BPentium 4, MIPS R12K, IBM, Power5
- CMIPS and ARM
- DTI C6x
175Examples of superscalar(static):
- AMIPS and ARM
- BPentium 4, MIPS R12K, IBM, Power5
- CItanium
- DTI C6x
176Examples of superscalar(dynamic) :
- ANone at the present
- BPentium 4, MIPS R12K, IBM, Power5
- CMIPS and ARM
- DTI C6x
177Examples of VLIW/LIW:
- ATI C6x
- BMIPS and ARM
- CItanium
- DPentium 4, MIPS R12K, IBM, Power5
178A branch-prediction cache that stores the predicted address for the next instruction after a
branch- Abranch-target buffer
- Bdata buffer
- Cframe buffer
- Doptical buffer
179Buffering the actual target instructions allows us to perform an optimization which called:
- Abranch folding
- BBranch prediction
- CTarget instructions
- DTarget address
180Which is not the function of integrated instruction fetch unit:
- AInstruction memory commit
- BIntegrated branch prediction
- CInstruction prefetch
- DInstruction memory access and buffering
181What is the simple technique that predicts whether two stores or a load and a store refer to
the same memory address:- AAddress aliasing prediction
- BBranch prediction
- CIntegrated branch prediction
- DDynamic branch prediction
182How to decrypt RISC?
- AReduced Instruction Set Computer
- BRecall Instruction Sell Communication
- CRename Instruction Sequence Corporation
- DRed Instruction Small Computer
183The ideal pipeline CPI is a measure of …
- Athe maximum performance attainable by the implementation
- Bthe maximum performance attainable by the instruction
- Cthe minimum performance attainable by the implementation
- Dthe minimum performance attainable by the instruction
184What is the Pipeline CP = ?
- Adeal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls
- Bdeal pipeline CPU + Data hazard stalls + Control stalls
- Cdeal pipeline CPU + deal pipeline CPI + Data hazard stalls + Control stalls
- DStructural stalls + Data hazard stalls + Control stalls
185The simplest and most common way to increase the ILP is …?
- Ato exploit parallelism among iterations of a loop
- Bto exploit minimalism among iterations of a loop
- Cto destroy iterations of a loop
- Dto decrease the minimalism of risk
186The simplest and most common way to increase the ILP is to exploit parallelism among
iterations of a loop. How is often called?- Aloop-level parallelism
- Bexploit-level parallelism
- Chigh-level minimalism
- Dlow-level minimalism
187In parallelism have three different types of dependences, tagging him:
- Adata dependences , name dependences , and control dependences
- Bdata dependences , name dependences , and surname dependences
- Cdatagram dependences , name dependences , and animal dependences
- Dno correct answers
188What is Name dependence?
- Aname dependence occurs when two instructions use the same register or memory location
- Bname dependence occurs when five or more instructions use the same register or memory location
- Cname dependence occurs when instructions use the same name
- DAll answers is correct
189When occurs an output dependence?
- AWhen i and instruction j write the same register or memory location
- Bwhen i and instruction j write the same name
- Cwhen i and instruction j write the same adress or memory location
- DAll answers is correct
190What is RAW (read after write)?
- Awhen j tries to read a source before i writes it, so j incorrectly gets the old value
- Bwhen i tries to read a source before j writes it, so j correctly gets the old value
- Cwhen j tries to write a source before i writes it
- Dwhen a tries to write a source before b read it, so a incorrectly gets the old value
191What is given is not a hazard?
- ARAR
- BWAR
- CWAW
- DLOL
Informationen
- Beschreibung
- PC Architecture Quiz am PC, erstellt von Csse 1502 am 12/03/2018.
- Autor
- Csse 1502
- Sprache
- English
- Aufrufe
- 35
- Schlagwörter
- Bewertung
- Noch keine Bewertungen Bewerte dieses Quiz