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Karteikarten

Xilinx FPGA - Lecture 2

Konstantinos Athanasiou Electronics Englisch 17 Karten

Karten in diesem Stapel (17)

  1. 1What Xilinx FPGAs contain ? (Basic resources)-Slices (grouped into CLBs):
    Contain combinatorial logic and register resources
    -IOBs (Input Output Blocks):
    Interface between the FPGA and the outside world
    -Programmable Interconnect
    - Other resources:
    Memory,Multipliers
  2. 2How many LUTs contain the CLBs of the XIlinx Virtex-4 FPGAs?CLBs:
    -4 LUTs /RAM (4-input)
    -4 LUTs (4-input)
    -8 FF/Latches
  3. 3What is the main purpose of the CLBs?Configuration memory bits controlled the routing in the interconnect. Software tool for place and routing controlled how logic is places in the CLBs and how routes are formed.
  4. 4Most of the delay in the FPGA concentrates in?The routing wires
    (Due to the complex routes)
    Up to 90% of the delay.
  5. 5How main slices contains a Virtex-IV?Four Slices:
    -Local routing provides feedback between slices in the same CLB, and it provides routing to neighboring CLBs
    -A switch matrix provides access to general routing resources
  6. 6State the slices pairs-Left-hand SLICEM:
    LUTs can be configured as logic, memory or SRL16
    -Right-hand SLICEL:
    LUT can be used as logic only
  7. 7State the basic elements of the Virtex-4 slice (L) architecture- Two logic function generators (LUTs)
    -Two storage elements
    -Multiplexers, carry logic and arithmetic gates
  8. 8LUTs also called?Function Generators (FGs)
  9. 9Delay through the LUT is .....?Constant
  10. 10What logic is stored in LUPs?Combinatorial Logic
  11. 11Which gate is used for single-level sum completion ? (Fast Carry Logic)XOR Gate
  12. 12Which gate is used for efficient multiply and add implementation ?AND Gate
  13. 13How many flexible sequential elements are exist in a CLB?Two in each slice; eight in each CLB
    (either flip-flops or latches)
  14. 14Each LUT can be configured as?A swift register:
    Serial in, Serial out
  15. 15State some of the Virtex-4 features- Distributed RAM and block RAM
    - Dedicated 18 x 18 multipliers in DSP blocks
    - Clock management resources
  16. 16The basic configuration element of a Xilinx FPGA is ...?A SRAM element
  17. 17The best way to implement a multiplier in a Virtex - 4 Xilinix FPGA is .....?Using a DSP slice

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Electronics (Embedded System) Karteikarten am Xilinx FPGA - Lecture 2, erstellt von Konstantinos Athanasiou am 30/09/2016.
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