Computer Science

Computer Science

1. 1.1.1 Structure and Function of the Processor

   • Architecture of Processor
     • Von Neumann
       • Von Neumann has 1 main memory that stores both instructions and data.
     • Harvard
       • Harvard contains 2 memories, 1 for Instructions and 1 for Data. This also means that there are 2 data buses.
     • Contemporary
       • Contemporary consists of one memory which holds both instructions and data, however there is an instruction cache and a data cache
     • Pipe-lining
       • Pipe-lining allows for the next instructions in code to be fetched while the previous instruction is being decoded and the instruction before that is being executed
   • Inside the CPU
     • ALU
       • Arithmetic & Logic Unit
         • This does any calculations (Such as 2+2) and logic that the CPU needs to do
     • Registers
       • ACC
         • Accumulator
       • PC
         • Program Counter
       • MDR
         • Memory Data Register
       • MAR
         • Memory Address Register
       • CIR
         • Current Instruction Register
     • Control Unit
       • manages how data moves around the CPU and memory. Responsible for decoding instructions
     • Clock
       • Everything happens on the beat of the clock, it orchestrates the FDE cycle
   • Factors that affect Performance
     • Clock Speed
       • If it's faster, the CPU can run more cycles faster
     • Register Size
       • 32/64 bit - How much data can be processed at one time.
     • Cores
       • May work on multiple tasks at once
     • Bus Width/Size
       • The bigger the bus, the more info it can transfer on 1 clock cycle
     • Cache
       • Contains programs/tasks that are often used for quicker access
   • Fetch, Decode, Execute Cycle
     • Effect on Registers
       • Check Attachments
         • Fetch, Decode, Execute
     • Effect of Buses

2. 1.1.2 Types of Processor

   • CISC
     • Larger Instruction Set – More instructions can be used when programming One instruction – equates to many FDE cycles Generally runs slower than RISC Uses a less memory to store intermediate results
       • Generally used by Desktop computers – however although intel x86 chips are CISC – they are becoming more “hybrid” using RISC architecture inside
   • RISC
     • Smaller Instruction Set – fewer instructions can be used One instruction – equates to one FDE cycle Generally runs faster than CISC Uses a little more memory to store intermediate results
       • Generally used by Smart phones, tablets, as uses low power.
   • GPU
     • A GPU is a form of co-processor that allows the compute-intensive task of generating graphics on a screen be offloaded from the CPU. Excellent at applying a Single Instruction, across Multiple items of Data (SIMD) - For example adjusting lighting on an object in a 3D game.
   • Multicore
     • Multicore CPUs are able distribute workload across multiple CPU cores, thus achieving significantly higher performance.
   • Parallel
     • The improvement in performance gained using a multicore processor is dependent on the software being able to being written to take advantage of the parallel processing capabilities.
   • Co- Processor
     • A co-processor is an extra processor to perform a specific task particularly well. It takes load off the main CPU and generally has limited functionality.