Computer Architecture

Computer Architecture

1. Function and Interconnection

   • Major components
     • CPU
     • I/O
       • Input Module: Accept data and convert them
       • Output Module: Means of reporting results
   • Instruction cycle
     • Fetch
       • Fetches instruction from mem.
       • PC holds address of next instruction
       • PC increments after each instructions
       • Fetched instruct. loaded into IR
       • Processor interprets and perform required action
         • Processor Mem.
         • Processor I/O
         • Data processing
         • Control
     • Interupts
       • Program
       • Timer
       • I/O
       • Hardware failure
   • Buses
     • Control
     • Address
     • Elements of bus design
       • Type
       • Method of Arbitration
         • Centralised, Distributed
       • Timing
         • Synch., Asynch.
       • Bus Width
       • Bus width
       • Data trans. type
   • P2P interconnection
     • QPI physical layer
     • QPI link layer
     • QPI routing layer
     • QPI protocol layer
   • PCI Express
     • Physical and logical arch.
     • PCIe physical layer
     • PCIe transaction layer
     • PCIe data link layer

2. Cache Memory

   • Memory hierarchy
   • Characteristics
     • Location
     • Capacity
     • Unit of transfer
   • principles
   • Elements of cache design
     • Addresses
     • Size
     • Mapping fuction
       • Address length = (s + w) bits| Number of addressable units = 2s+w words or bytes| Block size = line size = 2w words or bytes| Number of blocks in main memory = 2^(s+ w)/2^w = 2^s| Number of lines in cache = m = 2r |Size of tag = (s – r) bits
       • Because there are fewer cache lines than main memory blocks, an algorithm is needed for mapping main memory blocks into cache lines
         • Direct
         • Associative
         • Set associative
           • Number of lines in set = k Number of sets = v = 2^d| Number of lines in cache = m=kv = k * 2^d |Size of cache = k * 2^(d+w )words or bytes |Size of tag = (s – d) bits
       • Victim cache
         • Reduce conflict without affecting access time
     • Replacement Algorithm
       • Least recently used
       • FIFO
       • Least Frequently used
     • Write policy
       • Write through and write back
     • Line size
     • Number of caches
   • Method of accessing units of data
     • Sequential
     • Direct
     • Random
     • Assiociative
   • Multilevel vache
   • Unified vs Split caches

3. Internal Memory

   • Memory Cell Operation
     • Read
       • Select,Control, Data in
     • Write
       • Control, Sense, Select
   • Semiconductor Mem. types
     • RAM, ROM,PROM,EPROM,EEPROM,Flash mem.
       • ROM
         • Permanent pattern
         • No power source
         • No need to be loaded from 2nd storage
         • Data wired into the chip(Manufacturing)
         • Disadvantage
           • No room for error
           • Data insertion step includes a relatively large fixed cost
       • PROM
         • Less expensive
         • Nonvolatile
         • Writing process electrical
         • Flexible/Convinient
         • Attractive for high volume production runs
   • Dynamic Ram
     • SRAM
       • Uses same logic elements used in processor
       • Binary values are stored using traditional flip-flop logic gate configurations
       • Will hold its data as long as power is supplied to it
     • DRAM
       • Store data as charge on capacitor
       • Presence/absence of charge 1/0
       • Needs periodic refreshing
       • Charges leak away
   • Interleaved mem.
     • 1.DRAM
     • 2.Memory bank
     • 3.Banks are independent
     • 4. K banks request simultaneously
     • 5. Words are stored in different banks
   • Error correction
     • Hard failure
       • Permanent physical defect
     • Soft error
       • Random, non-destructive event that alters the contents of one or more memory cells
   • Advanced DRAM org.
     • SDRAM
       • Widely used
       • exchanges data with the processor synchronized to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states
       • send data once per bus clock cycle
     • DDR
       • can send data twice per clock cycle
     • RDRAM
       • delivers address and control information using an asynchronous block-oriented protocol
     • CDRAM
       • Integrates a small SRAM cache onto a generic DRAM chip

4. Computer Evolution and Performanc

   • First Generation:Vacuum tube
     • ENIAC
       • 5000 additions/min
       • 18000 vac. tubes
       • Plugging/unplugging cables
     • IAS
       • memory consists of 1000 storage locations (called words) of 40 bits each
       • data/instructions stored there
       • No. are represented in binary/each instruction is a binary code
   • Registers
     • (MBR): Contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit
     • (MAR): Specifies the address in memory of the word to be written from or read into the MBR.
     • (IR ): Contains the 8-bit opcode instruction being executed
     • (IBR): Employed to hold temporarily the right-hand instruction from a word in memory
     • (PC): Contains the address of the next instruction pair to be fetched from memory
     • (AC) and (MQ): holds temporarily operands and results of ALU operations.
   • Second Generation: Transitors
     • Introduced
       • complex arithmetic and logic units and control units
       • High level programming
       • Provision of system software
   • Third Generation: Integrated circuits
     • Single, self-contained transistor
     • Integrated circuit
       • Data storage,memory cells
       • Data processing,gates
       • Data movement
       • Control , signal
     • Moore's law
       • the number of transistors that could be put on a single chip was doubling every year
   • Later Generation:Semiconductor Memory Microprocessors
     • Microprocessor Speed
       • Pipelining
       • Branch prediction
       • Data flow analysis
       • Speculative execution
     • Performance balance
     • Improvements in chip
       • Increase HW speed of processor
       • Increase size/speed of cache
       • Change processor org. architecture
   • Microprocessor speed
     • Pipelining
       • movement of data or instructions into a conceptual pipe with all stages
     • Branch prediction
       • : The processor looks ahead in the instruction code fetched
     • Data flow analysis
       • processor analyzes which instructions are dependent on each other’s results, or data, to create an optimized schedule of instructions
     • Speculative execution
       • execute instructions ahead of their actual appearance in the program execution
   • Improvements in Chip Organization and Architecture
     • Increase hardware speed of processor
     • Increase size and speed of caches
     • Change processor organization and architecture
   • Problems with Clock Speed and Login Density
     • Power
     • RC delay
     • Memory latency
   • X86
     • Embedded Systems
     • Acorn RISC Machine (ARM)
     • System Performance Evaluation Corporation (SPEC)
       • Benchmark suite
       • SPEC