Quiz
Ch 9 True/False
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Fragen in diesem Quiz (13)
1A relocation register is used to check for invalid memory addresses generated by a CPU.
- ARichtig
- BFalsch
2Reentrant code cannot be shared.
- ARichtig
- BFalsch
3There is a 1:1 correspondence between the number of entries in the TLB and the number of entries in the page table.
- ARichtig
- BFalsch
4Hierarchical page tables are appropriate for 64-bit architectures.
- ARichtig
- BFalsch
5The ARM architecture uses both single-level and two-level paging.
- ARichtig
- BFalsch
6Fragmentation does not occur in a paging system.
- ARichtig
- BFalsch
7Hashed page tables are particularly useful for processes with sparse address spaces.
- ARichtig
- BFalsch
8Inverted page tables require each process to have its own page table.
- ARichtig
- BFalsch
9Without a mechanism such as an address-space identifier, the TLB must be flushed during a context switch.
- ARichtig
- BFalsch
10A 32-bit logical address with 8 KB page size will have 1,000,000 entries in a conventional page table.
- ARichtig
- BFalsch
11Hashed page tables are commonly used when handling addresses larger than 32 bits.
- ARichtig
- BFalsch
12The x86-64 bit architecture only uses 48 of the 64 possible bits for representing virtual address space.
- ARichtig
- BFalsch
13Mobile operating systems typically support swapping.
- ARichtig
- BFalsch
Informationen
- Beschreibung
- Computer Science Quiz am Ch 9 True/False, erstellt von Storm Davis am 26/04/2019.
- Autor
- Storm Davis
- Sprache
- English
- Aufrufe
- 7
- Verlauf
- Erstellt am 26 Apr 2019 · aktualisiert am 26 Apr 2019
- Schlagwörter
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