Quiz
[CPSC313 Final] Midterm 1 Quiz
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Fragen in diesem Quiz (42)
1[blank_start]FETCH[blank_end]: Load instruction from memory, determine its length and format, and separate it into individual
pieces.- AFETCH
- BDECODE
- CEXECUTE
- DMEMORY
- EWRITE BACK
2[blank_start]WRITE BACK[blank_end]: Write values to register file.
- AWRITE BACK
- BFETCH
- CEXECUTE
- DDECODE
- EMEMORY
3[blank_start]DECODE[blank_end]: Determine register numbers that will be read from and written to the register file. Read values
from register file.- ADECODE
- BFETCH
- CMEMORY
- DWRITE BACK
- EEXECUTE
4[blank_start]MEMORY[blank_end]: Read or write data operands from/to memory.
- AMEMORY
- BEXECUTE
- CDECODE
- DFETCH
- EWRITE BACK
5[blank_start]EXECUTE[blank_end]: Do math. Set condition codes. Determine whether conditional jumps are taken or whether
conditional moves move.- AEXECUTE
- BDECODE
- CFETCH
- DMEMORY
- EWRITE BACK
6Why is the memory stage after the execute stage?
- ASo that execute can perform address calculations. If E was before M then mrmovl and rmmovl could not use base plus displacement addressing and pushl would be able to write to esp minus 4.
- BSo that we can perform math on register values. If M was before E, none of the ALU instructions (eg., addl) would work.
- CSo that we can write a value from memory into a calculation. If M was before E, mrmovl and popl would not work.
7Why is the execute stage after the decode stage?
- ASo that we can perform math on register values. If E was before D, none of the ALU instructions (e.g., addl) would work.
- BSo that execute can perform address calculations. If E was before D, then mrmovl and rmmovl could not use base plus displacement addressing and pushl would be able to write to esp minus 4.
- CSo that we can write a value from a register into the ALU. If E was before D, mrmovl and popl would not work.
8Why is the write-back stage after the memory stage?
- ASo that we can write a value from memory into a register. If W as before M, mrmovl and popl would not work.
- BSo that we can perform math on memory values. If W was before M, none of the ALU instructions (e.g., addl) would work.
- CSo that memory can perform address calculations. If W was before M then mrmovl and rmmovl could not use base plus displacement addressing and pushl would be able to write to esp minus 4.
9RISC instruction sets do not allow an ALU operation (e.g., addl) to read from memory.
Explain how the structure of the pipeline leads to this restriction.- AThe memory stage comes after the execute stage and so by the time we’ve read a value from memory it is too late to do math on it.
- BThe memory stage comes after the write back stage and so by the time we’ve read a value from memory it is too late to write it back.
- CThe execute stage comes after the decode stage and so by the time we've done math/logical operations it is too late to retrieve register values.
- DThe execute stage comes after the fetch stage and so by the time we've done math/logical operations it is too late to parse the instruction.
10RISC instruction sets do not allow an ALU operation (e.g., addl) to read from memory.
Describe how the pipeline could be modified to lift this restriction. You may not change the number
of pipeline stages or their basic function. Your revised pipeline does not need to be able to implement
every Y86 instruction (in fact it would not be able to) but it must be able to execute instructions like:
addl (%eax), %ebx #r[ebx] = r[ebx] + m[r[eax]]- ASwap the order of M and E so that M comes first.
- BSwap the order of M and W so that W comes first.
- CSwap the order of E and D so that E comes first.
- DSwap the order of E and F so that E comes first.
11RISC instruction sets do not allow an ALU operation (e.g., addl) to read from memory. But in the last question there was a revision made to allow this.
This revised pipeline must place some restrictions on the revised ISA that it implements. One of
the impacts is on mrmovl and rmmovl. Describe the problem and modify the instructions so that
they will work with the new pipeline. Note that the revised versions need not be as powerful as the
original ones, but they must still load and store between memory and a register.- AWe must eliminate base plus displacement addressing. The only addressing mode allowed would be like this mrmovl (%eax), %ebx.
- BWe must add a check when instructions move from E to M to make sure there is mrmovl and rmmovl are handled properly.
- CWe must add a check when instructions move from D to E to make sure there is mrmovl and rmmovl are handled properly.
- DWe must eliminate memory reads from the memory stage. The only addressing mode allowed would be like this mrmovl %ebx, (%eax).
12Consider the following five-stage pipeline with stage delays (including overheads) of 34 ps,
42 ps, 75 ps, 50 ps and 18 ps. (NOTE: To simplify the math, you can give answers like 1/100 instead of 0.01 or 1+2+3 instead of 6. Be sure to include units.)
What is the maximum clock rate (i.e., fastest) acceptable for this pipeline?
(1 [blank_start]cycle[blank_end]) / ([blank_start]75[blank_end] ps) = [blank_start]1000[blank_end]/75 [blank_start]GHZ[blank_end]- Acycle
- B75
- Cinstruction
- Ddelay
- E42
- F50
- G18
- H1000
- I100
- J10
- KGHZ
- LMHZ
13Consider the following five-stage pipeline with stage delays (including overheads) of 34 ps,
42 ps, 75 ps, 50 ps and 18 ps. (NOTE: To simplify the math, you can give answers like 1/100 instead of 0.01 or 1+2+3 instead of 6. Be sure to include units.)
1/[blank_start]75[blank_end] [blank_start]instructions[blank_end] per [blank_start]pico second[blank_end].- Ainstructions
- B75
- C42
- D50
- E18
- Fcycles
- Gpico second
- Hmilli second
- Imicro second
- Jsecond
14Consider the following five-stage pipeline with stage delays (including overheads) of 34 ps,
42 ps, 75 ps, 50 ps and 18 ps. (NOTE: To simplify the math, you can give answers like 1/100 instead of 0.01 or 1+2+3 instead of 6. Be sure to include units.)
What, if anything, might cause the actual throughput of programs to be lower than this maximum?
[blank_start]Bubbles from hazards[blank_end].- ABubbles from hazards
- BLarger instructions
- CSmaller instructions
15Consider the following five-stage pipeline with stage delays (including overheads) of 34 ps,
42 ps, 75 ps, 50 ps and 18 ps. (NOTE: To simplify the math, you can give answers like 1/100 instead of 0.01 or 1+2+3 instead of 6. Be sure to include units.)
[blank_start]75*5ps[blank_end]- A75*5ps
- B18*5ps
- C75ps+50ps+34ps+42ps+18ps
- D34*5ps
- E42*5ps
- F50*5ps
16Consider the following piece of Y86 assembly code.
[0] addl %eax, %ebx
[1] irmovl $1, %eax
[2] mrmovl %(ebx), %ebx
[3] addl %ebx, %eax
List all of the anti dependencies present in this code. Indicate the instructions and registers or memory locations involved.- A0 and 1 on %eax
- B0 and 2 on %ebx
- C0 and 3 on %eax
- D1 and 3 on %eax
- E2 and 3 on %ebx
17Consider the following piece of Y86 assembly code.
[0] addl %eax, %ebx
[1] irmovl $1, %eax
[2] mrmovl %(ebx), %ebx
[3] addl %ebx, %eax
List all of the causal dependencies present in this code. Indicate the instructions and registers or memory locations involved.- A1 and 3 on %eax
- B2 and 3 on %ebx
- C0 and 2 on %ebx
- D0 and 1 on %eax
- E0 and 3 on %eax
18Consider the following piece of Y86 assembly code.
[0] addl %eax, %ebx
[1] irmovl $1, %eax
[2] mrmovl %(ebx), %ebx
[3] addl %ebx, %eax
List all of the output dependencies present in this code. Indicate the instructions and registers or memory locations involved.- A0 and 1 on %eax
- B0 and 2 on %ebx
- C0 and 3 on %eax
- D1 and 3 on %eax
- E2 and 3 on %ebx
19Consider the following piece of Y86 assembly code.
[0] addl %eax, %ebx
[1] irmovl $1, %eax
[2] mrmovl %(ebx), %ebx
[3] addl %ebx, %eax
List all of the data hazards present in this code for the Y86, five stage pipeline- A0 and 1 on %eax
- B0 and 2 on %ebx
- C0 and 3 on %eax
- D1 and 3 on %eax
- E2 and 3 on %ebx
20Consider the following piece of Y86 assembly code.
[0] addl %eax, %ebx
[1] irmovl $1, %eax
[2] mrmovl %(ebx), %ebx
[3] addl %ebx, %eax
For each hazard, indicate the total number of bubbles added by the Pipe-Minus. Remember that the stalls will carry over to the next instruction (i.e. if you stall in one, take it into consideration for the next)- A2 for (0 and 2 on %ebx)
- B2 for (0 and 1 on %eax)
- C0 for (1 and 3 on %eax) because 3 was stalled when 2 was stalled waiting for 0
- D0 for (2 and 3 on %ebx) because 3 was stalled when 2 was stalled waiting for 0
- E3 for (2 and 3 on %ebx)
- F3 for (1 and 3 on %ebx)
21Consider the following piece of Y86 assembly code.
[0] addl %eax, %ebx
[1] irmovl $1, %eax
[2] mrmovl %(ebx), %ebx
[3] addl %ebx, %eax
For each hazard, indicate the total number of bubbles added by the Pipe implementation.- A1 for (2 and 3 on %ebx)
- B1 for (0 and 2 on %ebx)
- C1 for (1 and 3 on %eax)
- D1 for (0 and 1 on %eax)
- E1 for (0 and 3 on %eax)
22Describe the implementation of the following new instruction for Y86 Seq as you did in Homework 2. This instruction is similar to mrmovl except that it adds 4 to rB and does not have static-displacement operand. It would be useful, for example, for iterating over an array of integers.
Syntax:
mrmovincl (rB), rA
Semantics:
r[rA] <= m[r[rB]]
r[rB] <= r[rB] + 4
Memory Layout:
| 5 | F | rA | rB |
Describe each stage using a relaxed syntax similar as shown below. The Fetch and PC Update stages are complete. List only the code that would be added for this instruction.
Fetch:
f.iCd = m[F.pc] >> 4
f.iFn = m[F.pc] & 0xF
f.rA = m[F.pc+1] >> 4
f.rB = m[F.pc+1] & 0xF
f.valP = F.pc + 2
Decode:
d.[blank_start]srcA[blank_end] = R_NONE
d.[blank_start]srcB[blank_end] = D.rB
d.dstE = D.[blank_start]rB[blank_end]
d.[blank_start]dstM[blank_end] = D.rA
d.[blank_start]valB[blank_end] = r[d.srcB]
Execute:
[blank_start]e.aluA[blank_end] = [blank_start]4[blank_end]
e.[blank_start]aluB[blank_end] = E.valB
e.aluFun = [blank_start]A_ADD[blank_end]
e.valE = [blank_start]4 + E.valB[blank_end]
Memory:
m.[blank_start]valM[blank_end] = [blank_start]m4[blank_end][M.valB]
Write Back:
r[W.dstE] = W.[blank_start]valE[blank_end]
r[W.dstM] = W.valM
PC Update:
w.pc = W.valP- AsrcA
- BsrcB
- CrB
- DdstM
- EvalB
- Fe.aluA
- G4
- H4 + E.valB
- IA_ADD
- JaluB
- KvalM
- Lm4
- Mm1
- NvalE
23Write Y86 assembly code that computes the sum of an array of integers where the address of
the array is stored in %ebx and the length of the array is in %ecx. Place the sum in %eax.
[blank_start]irmovl $0[blank_end], %eax
[blank_start]irmovl $1[blank_end], %edi
[blank_start]irmovl $4[blank_end], %esi
andl [blank_start]%ecx, %ecx[blank_end] # set CC for n
[blank_start]jle[blank_end] L1 # goto L1 if i<=0
L0:
mrmovl ([blank_start]%ebx[blank_end]), [blank_start]%edx[blank_end] # edx = *a
addl %edx, [blank_start]%eax[blank_end] # eax = eax + *a
addl [blank_start]%esi, %ebx[blank_end] # a++
subl [blank_start]%edi, %ecx[blank_end] # n--
jg L0 # goto L0 if n > 0
L1:- Airmovl $0
- Birmovl $1
- Cirmovl $4
- D%ecx, %ecx
- Ejle
- F%ebx
- G%edx
- H%eax
- I%esi, %ebx
- J%edi, %ecx
24Answer these questions by saying what the specified feature is and why it is important. Your
explanation must refer to specific architectural feature(s) of the processor or memory hierarchy that are
designed to execute programs faster when the specified feature exists.
temporal locality- AExists when memory accesses are clustered together to nearby memory addresses. Caches exploit it by storing data in multi-byte blocks.
- BExists when the same memory location is accessed repeatedly. Caches exploit it by retaining recently accessed blocks in the cache.
- CExists between a pair of instructions when there are no dependencies between them and thus their execution order does not matter. Pipelined (and super-scalar) processor architectures exploit it.
- DExists when programs explicitly indicate that threads of execution can be executed in parallel by either directly or indirectly creating multiple threads that can execute con-currently. Multi-core processors (and hyper-threading) exploit it.
25Answer these questions by saying what the specified feature is and why it is important. Your
explanation must refer to specific architectural feature(s) of the processor or memory hierarchy that are
designed to execute programs faster when the specified feature exists.
temporal locality- AExists when memory accesses are clustered together to nearby memory addresses. Caches exploit it by storing data in multi-byte blocks.
- BExists when the same memory location is accessed repeatedly. Caches exploit it by retaining recently accessed blocks in the cache.
- CExists between a pair of instructions when there are no dependencies between them and thus their execution order does not matter. Pipelined (and super-scalar) processor architectures exploit it.
- DExists when programs explicitly indicate that threads of execution can be executed in parallel by either directly or indirectly creating multiple threads that can execute con-currently. Multi-core processors (and hyper-threading) exploit it.
26Answer these questions by saying what the specified feature is and why it is important. Your
explanation must refer to specific architectural feature(s) of the processor or memory hierarchy that are
designed to execute programs faster when the specified feature exists.
instruction-level parallelism- AExists when memory accesses are clustered together to nearby memory addresses. Caches exploit it by storing data in multi-byte blocks.
- BExists when the same memory location is accessed repeatedly. Caches exploit it by retaining recently accessed blocks in the cache.
- CExists between a pair of instructions when there are no dependencies between them and thus their execution order does not matter. Pipelined (and super-scalar) processor architectures exploit it.
- DExists when programs explicitly indicate that threads of execution can be executed in parallel by either directly or indirectly creating multiple threads that can execute con-currently. Multi-core processors (and hyper-threading) exploit it.
27Answer these questions by saying what the specified feature is and why it is important. Your
explanation must refer to specific architectural feature(s) of the processor or memory hierarchy that are
designed to execute programs faster when the specified feature exists.
thread-level parallelism- AExists when memory accesses are clustered together to nearby memory addresses. Caches exploit it by storing data in multi-byte blocks.
- BExists when the same memory location is accessed repeatedly. Caches exploit it by retaining recently accessed blocks in the cache.
- CExists between a pair of instructions when there are no dependencies between them and thus their execution order does not matter. Pipelined (and super-scalar) processor architectures exploit it.
- DExists when programs explicitly indicate that threads of execution can be executed in parallel by either directly or indirectly creating multiple threads that can execute con-currently. Multi-core processors (and hyper-threading) exploit it.
28Polymorphic dispatch common to object-oriented languages like Java is implemented using a
double-indirect call instruction that reads an address from memory and then jumps to it. Explain why it is
challenging to implement such an instruction without stalling in a pipelined processor.- AThe address of the next instruction to execute after the call is not known to the pipeline until the call instruction exits the memory stage and so predicting which instructions should be F, D, and E at this point is impossible without retaining execution history.
- BThe address of the next instruction to execute after the call is not known to the pipeline until the call instruction exits the decode stage and so predicting which instructions should be in F at this point is impossible without retaining execution history.
- CThe address of the next instruction to execute after the call is not known to the pipeline until the call instruction exits the execute stage and so predicting which instructions should be in F and D at this point is impossible without retaining execution history.
- DThe address of the next instruction to execute after the call is not known to the pipeline until the call instruction exits the write back stage and so predicting which instructions should be in F, D, E, and M at this point is impossible without retaining execution history.
29Consider the following instruction-execution frequencies for a program running on the standard
Y86 Pipe processor. The table shows, for example, that 7% of all instructions executed read the value of a register immediately after the preceding instruction modified that register by writing into it a value that came from memory.
7%|read register immediately after an instruction writes into that register a value it reads from memory
6%|read register immediately after an instruction writes into that register a value computed in Execute
12%|conditional jump that is taken
8%|conditional jump that is not taken
5%|call
5%|ret
57%|the remaining introduce no bubbles
What is the CPI for this execution? [blank_start]1.38[blank_end]- A1.38
30Consider the following instruction-execution frequencies for a program running on the standard
Y86 Pipe processor. The table shows, for example, that 7% of all instructions executed read the value of a register immediately after the preceding instruction modified that register by writing into it a value that came from memory.
7%|read register immediately after an instruction writes into that register a value it reads from memory
6%|read register immediately after an instruction writes into that register a value computed in Execute
12%|conditional jump that is taken
8%|conditional jump that is not taken
5%|call
5%|ret
57%|the remaining introduce no bubbles
What is the throughput of this execution on a 3-Ghz processor (i.e., 3 x 10^9 cycles per second?
3 x 10^9 instructions / [blank_start]1.38[blank_end] second- A1.38
31In this question you will consider adding a new stage to Y86 Pipe between D and E called M0 and renaming the existing M stage to M1. The resulting pipeline thus looks like this F-D-M0-E-M1-W. For the first five questions, M0 does all memory reads and M1 does all memory writes (thus allowing ALU instructions to operate on values read from memory; e.g., “addl (%eax), %ebx”. Of course, this does require dropping the base-plus-displacement addressing mode for these instructions, but we will ignore this.
This design introduces a new hazard (for the new memory-ALU instructions it enables). Describe it.
There is now a [blank_start]causal[blank_end] hazard on memory if two instructions access the same memory location, the
first one is a [blank_start]write[blank_end] and the second [blank_start]a read[blank_end], and they are not separated by at least [blank_start]two[blank_end] other instructions.- Acausal
- Boutput
- Canti
- Dwrite
- Eread
- Fa read
- Ga write
- Htwo
- Ithree
32In this question you will consider adding a new stage to Y86 Pipe between D and E called M0 and renaming the existing M stage to M1. The resulting pipeline thus looks like this F-D-M0-E-M1-W. For the first five questions, M0 does all memory reads and M1 does all memory writes (thus allowing ALU instructions to operate on values read from memory; e.g., “addl (%eax), %ebx”. Of course, this does require dropping the base-plus-displacement addressing mode for these instructions, but we will ignore this.
When this hazard can be resolved by data forwarding, indicate the stage to which data is forwarded and state whether it is forward to the beginning or end of that stage.
[blank_start]End of M0[blank_end]- AEnd of M0
- BEnd of M1
- CEnd of D
- DEnd of E
33In this question you will consider adding a new stage to Y86 Pipe between D and E called M0 and renaming the existing M stage to M1. The resulting pipeline thus looks like this F-D-M0-E-M1-W. For the first five questions, M0 does all memory reads and M1 does all memory writes (thus allowing ALU instructions to operate on values read from memory; e.g., “addl (%eax), %ebx”. Of course, this does require dropping the base-plus-displacement addressing mode for these instructions, but we will ignore this.
When this hazard can be resolved by data forwarding, indicate the stage or stages from
which data is forwarded and state whether it is forwarded from the beginning or end of those stage(s).
[blank_start]End of E and end of M1[blank_end].- AEnd of E and end of M1
- BEnd of M0 and end of E
- CEnd of D and end of M0
- DEnd of M1 and end of W
34In this question you will consider adding a new stage to Y86 Pipe between D and E called M0 and renaming the existing M stage to M1. The resulting pipeline thus looks like this F-D-M0-E-M1-W. For the first five questions, M0 does all memory reads and M1 does all memory writes (thus allowing ALU instructions to operate on values read from memory; e.g., “addl (%eax), %ebx”. Of course, this does require dropping the base-plus-displacement addressing mode for these instructions, but we will ignore this.
Does this hazard ever require stalling? Explain.
[blank_start]No[blank_end]. The value needed by the memory read is [blank_start]known[blank_end] by the end of [blank_start]E[blank_end] and it is [blank_start]not needed[blank_end] until the end of [blank_start]M0[blank_end].- ANo
- BYes
- Cknown
- Dunknown
- EE
- FF
- GD
- HM
- IW
- JM1
- KM0
- Lnot needed
- Mneeded
35In this question you will consider adding a new stage to Y86 Pipe between D and E called M0 and renaming the existing M stage to M1. The resulting pipeline thus looks like this F-D-M0-E-M1-W. For the first five questions, M0 does all memory reads and M1 does all memory writes (thus allowing ALU instructions to operate on values read from memory; e.g., “addl (%eax), %ebx”. Of course, this does require dropping the base-plus-displacement addressing mode for these instructions, but we will ignore this.
Does this new design improve the performance (i.e. reduce stalls) for any of the original Y86 instructions? Explain.
[blank_start]Yes[blank_end]. It [blank_start]eliminates the[blank_end] stall associated with the load-use hazard because the load from memory [blank_start]will now[blank_end] be performed in [blank_start]M0[blank_end] and [blank_start]can thus[blank_end] be forwarded to D [blank_start]without[blank_end] stalling.- AYes
- BNo
- Celiminates the
- Dcreates a
- Ewill now
- Fnow has to
- GM0
- HM1
- Ican thus
- Jmust
- Kwithout
- Lwith
36In this question you will consider adding a new stage to Y86 Pipe between D and E called M0 and renaming the existing M stage to M1. The resulting pipeline thus looks like this F-D-M0-E-M1-W. For the first five questions, M0 does all memory reads and M1 does all memory writes (thus allowing ALU instructions to operate on values read from memory; e.g., “addl (%eax), %ebx”. Of course, this does require dropping the base-plus-displacement addressing mode for these instructions, but we will ignore this.
Finally, consider a different design in which M0 and M1 can both read and write memory (and additions to the instruction set to fully utilize this capability). Does this new design introduce the possibility of new hazards?
Check all that apply.- AYes. It introduces the possibility of hazards on both output and anti dependencies for access to memory.
- BYes. Two instructions could be writing to the same memory location, one in M0 and one in M1, which creates a hazard
- CYes. One instruction could be writing a location in M0 that is being read by another instruction in M1, which creates a hazard.
- DYes. It introduces the possibility of extra causal-hazards for access to memory.
- ENo. Now that M0 and M1 have both functions, the regular Pipe implementation's data forwarding and load-use prevention will catch the same hazards that would be present in this implementation.
37Consider how to handle the hazards associated with the following new instruction added to Y86 Pipe.
cmrmovlXX D(rB), rA
Its iCd is I_CMR and it has the following semantics where XX is one of (le, l, e, ne, ge, g):
r[rA] <= m[D+r[rB]] if condition codes indicate that condition XX holds
When answering this question, use a simplified syntax for accessing pipeline-stage registers that leaves out .get() and .set() etc. But be sure to correctly capitalize the pipeline id.
Give the complete data-forwarding logic for d.srcA for this instruction (and only this one) as it would appear in the DECODE stage (just srcA).
if (d.srcA != R_NONE) {
---if (d.src == [blank_start]M.dstM[blank_end] && [blank_start]M.cnd[blank_end])
------[blank_start]d[blank_end].valA = [blank_start]m.valM[blank_end];
---else if (d.srcA == [blank_start]W.dstM[blank_end] && W.cnd)
------[blank_start]d.valA[blank_end] = [blank_start]W.valM[blank_end];
---else
------d.[blank_start]valA[blank_end] = [blank_start]r[d.srcA][blank_end];- AM.cnd
- BM.dstM
- Cd
- DD
- Em.valM
- FW.dstM
- GW.valM
- Hr[d.srcA]
- Id.valA
- JvalA
38Consider how to handle the hazards associated with the following new instruction added to Y86 Pipe.
cmrmovlXX D(rB), rA
Its iCd is I_CMR and it has the following semantics where XX is one of (le, l, e, ne, ge, g):
r[rA] <= m[D+r[rB]] if condition codes indicate that condition XX holds
When answering this question, use a simplified syntax for accessing pipeline-stage registers that leaves out .get() and .set() etc. But be sure to correctly capitalize the pipeline id.
Give the complete pipeline-control logic for this instruction (and only this one) that would stall the
pipeline when and if necessary.
if (d.srcA != R_NONE && d.srcA == E.[blank_start]dstM[blank_end] && e.cnd) {
---[blank_start]f[blank_end].stall = true;
---[blank_start]d[blank_end].[blank_start]stall[blank_end] = true;
---[blank_start]e[blank_end].bubble = true;
}- Astall
- Bf
- Cd
- De
- Em
- Fw
- GdstM
- HdstE
39Answer these questions that consider changing an existing cache hierarchy to achieve a specific goal. In each case, describe a single change that you think would be most effective in achieving the stated goal. If there are multiple changes that you think would be equally effective, just describe one of them.
Improve the performance of programs that have significant spatial locality.- AIncrease block size.
- BIncrease cache size.
- CIncrease set-associativity.
- DDecrease cache size (or decrease set-associativity).
40Answer these questions that consider changing an existing cache hierarchy to achieve a specific goal. In each case, describe a single change that you think would be most effective in achieving the stated goal. If there are multiple changes that you think would be equally effective, just describe one of them.
mprove the performance of programs that have a significant number of capacity misses.- AIncrease block size.
- BIncrease cache size.
- CIncrease set-associativity.
- DDecrease cache size (or decrease set-associativity).
41Answer these questions that consider changing an existing cache hierarchy to achieve a specific goal. In each case, describe a single change that you think would be most effective in achieving the stated goal. If there are multiple changes that you think would be equally effective, just describe one of them.
Improve the performance of programs that have a significant number of conflict misses.- AIncrease block size.
- BIncrease cache size.
- CIncrease set-associativity.
- DDecrease cache size (or decrease set-associativity).
42Answer these questions that consider changing an existing cache hierarchy to achieve a specific goal. In each case, describe a single change that you think would be most effective in achieving the stated goal. If there are multiple changes that you think would be equally effective, just describe one of them.
Improve the performance of programs that have a significant number of cache hits.- AIncrease block size.
- BIncrease cache size.
- CIncrease set-associativity.
- DDecrease cache size (or decrease set-associativity).
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- Beschreibung
- CS313 Quiz am [CPSC313 Final] Midterm 1 Quiz, erstellt von Zim Brightwood am 12/12/2016.
- Autor
- Zim Brightwood
- Sprache
- English
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