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Hardware

Christian Müller Alemán 29 fichas

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  1. 1Cache- Processors use high-speed memory caches to reduce the cost of reading and writing to RAM.
    - The Cache is much faster than RAM.
    - has improved performance by keeping local copies of data in the cache
    - cache lines are read if data is requested. Read some data in advance because of possible future cache hit.
  2. 2Cache - cache hitData is already in the cache and can be accessed quickly
  3. 3Cache - cache missData is not in the cache and must be loaded from RAM
  4. 4Cache - cache lines- Cache lines are read if data is requested
    - Cache reads some data in advance for a possible future cache hit
  5. 5Cache - direct mapping- has limitations
    - beter performance with an n-way set associative cache. A RAM adress can map to n cache lines
  6. 6Cache - What replacement policy should be used?- Problem is that it must predict which existing entry is least likely to be used in the future
    - There is no perfect way to choose the right policy but the most popular one is the least-recently used which replaces least recently accessed entry
  7. 7Cache - write policieswrite-through: every write to the cache cause a write to main memory
    write-back: writes are not immediately mirrored to main memory but instead the cache marks locations as dirty which have been written over.
  8. 8Multilevel Caches- cache hits and misses can happen on multiple levels
    Instruction Cache: pre-loads executable machine code
    Data Cache: Speeds-up reading and writing to main RAM
  9. 9How to avoid Instruction Cache Miss?Use local instructions instead of function calls inside your code.
  10. 10How to avoid Data Cache Miss????
  11. 11Multicore CPUs - Moore's Law- In history of computing hardware the number of transistors in a dense integrated circuit has doubled approximately every 2 years
    - this no longer means improved speed
    (what happened was more force was added to the cpu)
    -more transistors means that the processor is more complex & smarter
  12. 12Multicore CPUs- each core has its own private L1 cache
    - multiple cores might share L2 cache, L3 cache and RAM
    - it is important to maintain cache coherency (data in the caches must match with the contents of RAM)
  13. 13Multicore CPUs - common cache coherency protocollsMESI and MOESI
  14. 14Multicore CPUs - Hyperthreading- are not virtual CPU calls but instead just physical calls with 2 architecture states each
    - context switches between the 2 running threads are extremely fast because both their execution resources can be stored on chip
  15. 15CPU basicsCPUs work by doing the same thing multiple times
    - multiplication happens with repeated additions
    - division works with repeated substractions
    - design structure of a CPU is mostly for minimizing idle time
    - in a CPU commands are pipelined in a ring buffer and handed over to the ALUs and FPUs
  16. 16CPU basics - clock ratethe number of pulses per second generated by an oscillator that sets the tempo for the processor (4.0 GHz)
  17. 17CPU basics - registers- are small amounts of storage available for data used for aithmetic, manipulation or testing by machine instructions
    - the size of a register define with how much data the processor can work at one time
  18. 18CPU basics - control unitfetches, decodes and sends instructions
  19. 19CPU basics - Arithmetic Logic Unit (ALU)ALU carries out integer math
  20. 20CPU basics - Floating Point Unit (FPU)FPU carries out floating point math
  21. 21CPU basics - Bus Interface Unit (BUI)sends data/instructions to L1 caches
  22. 22CPU basics - Branch Target Buffer (BTB)compares instructions with previous ones for potential reuse, especially concerned with branching
  23. 23CPU basics - fetch/decode unit3 decoders work in pallel and break down complex instructions into micro-operations
  24. 24CPU basics - Complex Instruction Set Computing (CISC)Instructions are complex and need to be decoded and converted
  25. 25CPU basics - Reduced ISC (RISC)Instructions are simple and ready to use
  26. 26Display synchronization (1/2)- monitor displays images at a certain refresh rate
    - screen tearing is a visual artifact in a video display where a display device shows information from 2 frames in a single screen (old picture and new picture in one)
    - to avoid this problem we can use VSync
  27. 27Display synchronization (2/2)- Gaming console's devs decide whether they use VSync or not
    - PCs are sometimes enforced by the games but most games let the player decide
  28. 28VSync- to avoid screen tearing VSync waits for the vertical blanking interval of the monitor before swapping buffers
    - Problem: lagging can happen when frame rate falls below the VSync frame rate cap (when performance improves the frame rate returns to 60 fps)
  29. 29NVIDIA's Adaptive VSyncUnlocks the frame rate when below the VSync cap and locks the frame rate when performance improves which leads to minimizing tearing.

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Fichas sobre Hardware, creado por Christian Müller el 19/02/2019.
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