Fichas
exam 3
Fichas del conjunto (10)
- 1LatencyThe number of stages in a pipeline or the number of stages between two instructions during execution.
- 2Branch predictionA method of resolving a branch hazard that assumes a given outcome for the branch and proceeds from that assumption rather than waiting to ascertain the actual outcome.
- 3Control hazard Also called branch hazardWhen the proper instruction cannot execute in the proper pipeline clock cycle because the instruction that was fetched is not the one that is needed; that is, the flow of instruction addresses is not what the pipeline expected.
- 4Pipeline stall: Also called bubbleA stall initiated in order to resolve a hazard.
- 5Load-use data hazard:A specific form of data hazard in which the data being loaded by a load instruction has not yet become available when it is needed by another instruction.
- 6Forwarding: Also called bypassingA method of resolving a data hazard by retrieving the missing data element from internal buffers rather than waiting for it to arrive from programmer-visible registers or memory.
- 7Data hazard: Also called a pipeline data hazard.When a planned instruction cannot execute in the proper clock cycle because data that is needed to execute the instruction is not yet available.
- 8Structural hazardWhen a planned instruction cannot execute in the proper clock cycle because the hardware does not support the combination of instructions that are set to execute.
- 9PipeliningAn implementation technique in which multiple instructions are overlapped in execution, much like an assembly line.
- 10Throughput: Also called bandwidthanother measure of performance, it is the number of tasks completed per unit time.
Información
- Descripción
- Computer Architecture Fichas sobre exam 3, creado por hassy saade el 07/05/2019.
- Creado por
- hassy saade
- Visitas
- 3
- Valoración