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A2 Hardware
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- 1What is a half adderA XOR gate and a AND gate. The XOR gate produces the Sum, the AND gate produces the carry. Half adders can be constructed using NANDs as well.
- 2What is a full adder?Full adders consist of two half adders that take in two bits as inputs and produce the sum bit; the OR gate takes in the carry bit and produces a carry new bit. The first XOR gate adds the two bits together to make a pre-sum. The pre-sum is input with the carry bit through the XOR gate from the second half adder to produce the final sum bit. The initial carry bit is ANDed with the presum to create a pre-sum carry, and is ORed with the result of ANDing the two inputs to create a final carry.
- 3What's the problem with half adders? What logic circuit construction solves it?Half adders can only take in two bits, therefore when adding binary that has more than one bit, a carry bit needs to be taken into account every time the bits are added. A full adder solves this problem.
- 4What's the difference between combinational circuits and sequential circuits?Combinational circuit: output is dependent only on input values
Sequential circuits: circuits which the output depends on the previous outputs and the inputs as well. - 5What are features of an SR flip flops?Can be implemented using NAND gates or NOR gates
Only when both S and R inputs flip does the value of Q and Q' flip
For NAND gates, the 'forbidden inputs' is S=R=0. This is because Q and Q' are meant to complement each other; this is invalid and puts the circuit in an unstable state.
For NOR SR: the retention/lock input is 0,0; it is 1,1 for NAND SR
For NOR: R input is above S input. Vice versa for NAND input - 6An application of SR flip flop and why they are suitable for that application?Used as bit memories, since the bit can either be in memory (q=1) or not (q=0). Its state can also be maintained.
- 7Features of JK flip flops?SR flop flops with two NAND/NOR gates and a clock
Clock is responsible for inputs to not happen simultaneously or not happen at the wrong time
When JK both =1, instead of being in an invalid state, Q inverses itself
Output only occurs when a clock is in its raising edge phase (clock pulse=true)
A JK NAND flip flop
RULE: J is always equal to subsequent Q, K is always equal to subsequent Q', and (Q)'=Q' - 8Describe the sum of product and product of sum rulesA rule that helps derive a boolean equation from its truth table
Rule:
look for 1s
Look at the two inputs that make it 1
If one of the input is 0, bar that input, vice versa. Multiply the two (barred or not) inputs
Do the same for all the inputs that produce a 1 output
Add up all the input pairs (which are products of two inputs) to produce a sum of products
e.g. A'B+CB. This is the sum of the two products A'B and CB.
Same as SOP rule, but for the POS rule look for 0s instead of 1s. Add up the inputs that make the output zeros. Multiply the pair of sums.
e.g. (A+B')(C'+A'): Product of the two sums A+B' and C'+A' - 9Give 5 differences between CISC and RISCInstructions in CISC are more complex than in RISC
CISC uses fewer registers than RISC
RISC is easier to pipeline as its instructions' lengths are fixed
CISC has more addressing modes
CISC is more compatible with HLL
CISC requires lots of memory access - 10What is instruction pipelining?This is instruction level parallelism. More than one instruction is using processor hardware per clock cycle. In each clock cycle, the instructions are likely to be at different stages of the FDE cycle.
- 11Why is pipelining advantageous?Reduces throughput time, which is the total amount of time it takes to complete all instructions
Maximises the use of processor hardware (RISC) for each clock cycle - 12Give one use for each of the following parallel processing computers: SISD, SIMD, MISD and MIMD.SISD: simple and basic computers
SIMD: GPUs
MISD: deciphering machines
MIMD: modern multicore computers, supercomputers - 13What is hard-wiring and what is its connection to the frequency at which main memory is accessed?Hard-wiring refers to instructions where control units utilise lots of registers and logic gates to handle instructions; there are no ROMs or microcode in such CUs. As a result, storage of instructions during FDE is stored mostly in registers, and so main memory is only accessed when instruction and data are retrieved and stored
- 14Explain microprogramming.Microprogramming: CU uses a ROM that has firmware (aka microcode aka microprogramming) to handle machine codes.
- 15What is firmware?Software written specifically for a hardware, and resides in the hardware's ROM. Firmware ensures the hardware functions correctly, and firmware can be updated so that the hardware's functions are also updated.
- 16What are the 4 types of parallelism, of which 3 is required by the syllabus?Instruction parallelism (pipelining)
Processor Parallelism (RISC and CISC)
Computer System Parallelism (MISD...) - 17What are the two ways in which RISC pipelining handles interrupts?On RISC machines, interrupts can happen while all five routines are being processed.
Fix:
1. Delete 4 previously entered instructions and begin normal interrupt handling
OR
2. Have a dedicated registers for each of the five parts of the processor that had a pipelining instruction. That way all instruction's data to be stored while interrupt is being processed.
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- Advanced Level (A- Level) (A2 Hardware) Computer Science Fichas sobre A2 Hardware , creado por TS P el 21/11/2016.
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