Fichas
Cache
Fichas del conjunto (26)
- 1What is a "block" or "line"?Unit for cache storing - Several words for ONE tag
- 2What is "caching"?Using small memories to store important data
- 3Types of caches?Fully-associative, set-associative, direct-mapped
- 4What is the "tag" for?Its the address of the data at that location in the cache. What address in memory the data came from.
- 5Why do we have 16 words/tag?We fetch more instructions at the same time -> probably load instructions we need later = spacial locality
- less space wasted on tags - 6Fully-ass cacheOnly one data per tag -> we can store any data anywhere. We search through it all every time we fetch data.
No bits for index. - 7Set-ass cachesEach cache block can go into 1 set (modulo mapping)
Each set can have multiple blocks - 8Direct-mapped cacheEach mem. location maps to 1 cache line with modulo
- 9How do you use address bits to determine which data to pick from cache?- Last 2: determine the byte within the word
- Next N: determine which word in the block
-Remaining 32-N-2: tag - 10Replacement policy for each cache-DM: only one block can be evicted
Set/fully-ass: choose random or choose least recently used - 11Write-back-write only to cache
-if its not there, read first
- need dirty bit to keep drack of data - 12Avarage mem access time AMAT(%hits)*(hit time)+(miss%)*(miss time + miss penalty)
- 13AMAT example; 1 cycle acc time (hit or miss) 100 cycle mem acc time I-cache has 1% miss, D-cache has 5% 33% har load/store instructionsFor I: (100%)*[99%*1+1%*(1+100)]=2 (For I-instructions we always access memory ->100% of instructions
For D: 33%*[95%*1 + 5%*(1+100)]=2
Total AMAT: 2+2=4 - 14What do we use the zero output for in the ALU?We use it when we do bne or beq. If the subtraction is zero -> equal!
- 15What is in an instruction?opcode, rs(src1), rt (src2), rd(dest), shamt och function
- 16Control hazards– Branches
– Branch delay slots - 17Data hazards– Stalling
– Forwarding - 18Structural hazardsWhen two need the same resource in the same cycle
- 19What is DRAM?main memory
• High density, low power, cheap, slow
• Needs to be “refreshed” regularly
• Cell: Uses capacitor to store charge which dissipates over time + switch
• Reading data uses up charge (must re-write after read)
Slow because it only has a charge on the capacitor driving the output. - 20What does D stand for in DRAM?Dynamic means that what’s written if ignored long enough will disappear.
- 21What is SRAM?CPU cache
• Low density, high power, expensive, fast
• Content lasts until power is lost
• Uses more transistors / bit
• Like a flip flop
• Cell: Two inverters in a feedback loop
Fast because it has a powered inverter driving the output - 22Memory hierarchyRegisters
Cache (SRAM)
Main Memory (DRAM)
Disk - 23How do you access data in the cache?1. Check if tag is in cache
2. Check if valid bit is 1
3. Read data from cache - 24How do you use bits for different caches?DM - First two bits - byte, next N bits for choosing word, next for index, rest 32-N is tag
Fully-ass: First two bits - byte, next N for word, NO INDEX, rest 32-N for tag
Set-ass: - 25What is stored IN the cache?the tag, data, valid or/and dirty bit. NOT index. The index points to the right place, but isn't stored in the cache
- 26How do you calculate overhead in cache?Tag + valid and/or dirty bit
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- Dark Fichas sobre Cache , creado por Emma Tysk el 24/05/2017.
- Creado por
- Emma Tysk
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