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Semiconductor Technology
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- 1Define Technology NodeThe minimum feature size of the manufacturing technology
and is typically the gate length of the transistor. - 2Silicon is a group IV element. Which group of dopants results in n-type silicon and which p-type silicon? Why?Group V (ie. Phosphorus) act as donors of electrons to create n-type silicon with electrons acting as the charge carriers.
Group III (ie. Aluminum) act as acceptors of electrons to create p-type silicon with "holes" acting as the charge carriers. - 3What are the two types of MOSFETs and which is the most common?Depletion Mode and Enhancement Mode.
The majority of MOSFETs manufactured are Enhancement Mode. - 4Explain the basic mechanism by which an Enhancement Mode NMOS operates.Positive charges at the Gate repel the positive charge carriers "Holes" in the p-type substrate, leaving the channel slightly negative. This process is called "Depletion".
As Vg is increased passed a threshold (Vt), free electrons are pulled from the n-type well at the source allowing current to flow from Drain to source. This process is called "Inversion". - 5In an NMOS, what is the relation between Vgs, charge layer thickness, and equivalent charge layer resistance?Vgs increases, thickness increases, resistance decreases.
- 6Define the Triode Region for a MOSFET and its usage.When the layer of charge underneath the gate extends continuously from source to drain.
Vds < Vgs - Vt
Id is linearly proportional to Vds
usage: closed switch / voltage controlled resistor. - 7Define the physical properties of a MOSFET in the Saturation Region.As Vds increases, the charge layer pinches of off at the drain side. When the charge layer is no longer continuous from source to drain the device enters the Saturation Region.
Vds > Vgs - Vt.
Id is non-linearly proportional to Vgs
Usage: Amplifier / voltage controlled current source. (Vgs controls Id) - 8Name the 3 types of intrinsic capacitances in a MOSFET.1. Gate-Channel: Split between Cgs & Cgd. significant during switching transitions. Cgd aka Miller Capacitance.
2. Gate Overlap
3. Depletion: Formed by the reverse-biased PN junctions. Csb & Cdb. - 9Name 3 common uses of Phase Locked Loops (PLL).- Clock recovery in communication systems
- Frequency synthesizers used in radios
- Demodulation of FM signals - 10Describe the basic composition of a CMOS cell.A complimentary NMOS gate for each PMOS gate and vice versa.
Each PMOS must have its input from the voltage source or another PMOS.
Each NMOS must have its input from ground or another NMOS. - 11How can billions of CMOS gates be chained together in series?The transistors' resistances are never exactly equal to zero or infinity, so Q will never exactly equal Vss or Vdd, but Q will always be closer to Vss than A was to Vdd (or vice versa if A were close to Vss).
- 12Why are CMOS more power efficient than standard NMOS?Static CMOS gates dissipate nearly zero power when idle.
CMOS dissipates power only when switching ("dynamic power").
NMOS logic dissipates power whenever the transistor is on. - 13Describe the transistor states in the 5 operating regions of a CMOS Inverter.Region A: 0 <= Vi < Vtn
PMOS - Triode | NMOS - Off
Region B: Vtn < Vi < Vdd/2
PMOS - Triode | NMOS - Saturation
Region C: Vi = Vo = Vdd/2
PMOS & NMOS - Saturation
Region D: Vdd/2 < Vi < Vdd - |Vtp|
PMOS - Saturation | Nmos - Triode
Region E: Vi > Vdd - |Vtp|
PMOS - Off | NMOS - Triode - 14Define Switching Power Dissipation in CMOS Inverter.The energy dissipated when the load capacitance is charged or discharged during circuit switching
- 15Define Short Circuit Power dissipation in CMOS inverter.Power loss due to a brief current flow from VDD to gnd during input transitions, when both NMOS and PMOS are simultaneously on
- 16Describe the effect of rise and fall times of input signals and load capacitances on short circuit power.• longer rise and fall times increase the duration for which both transistors are on leading to higher short circuit power.
• larger load capacitance can also affect transitions, indirectly influencing short circuit power consumption - 17What are the 3 types of Static Current Leakage.1. Sub-threshold
2. Gate-Tunneling
3. Reverse-bias P-N Junction - 18Define Sub-threshold Current Leakage.When the MOSFET is in the cutoff region, a small portion of energetic electrons will still diffuse from the source to the drain terminal, resulting in a small current.
- 19Describe the relationship between the supply voltage, dynamic power, threshold voltage, and subthreshold currents.- In modern technologies, the supply voltage is scaled to reduce dynamic power
- Threshold voltage is reduced to maintain drive strength at lower supply voltages
- Lower threshold voltage leads to an increase in sub-threshold currents - 20Define Gate-Tunneling Current Leakage.High electric field in the gate oxide layer leads to increased tunneling of electrons or holes from the body and source/drain overlap regions through the oxide into the gate.
- 21Describe how Gate-Tunneling leakage differs when the transistor is ON, compared to when it is OFF.• When the transistor is OFF, the leakage current flows through the overlap regions of the source and drain.
• When the transistor is ON, the leakage current flows through the overlap regions and the transistor channel making it generally higher in this case. - 22Define Reverse-bias P-N Junction Current Leakage and its cause.- Leakage due to a small current that flows in reverse-biased p-n junctions.
- Primarily caused by minority carriers, electrons in P-side and holes in N-side. - 23Describe how Reverse-bias P-N Junction Current Leakage is affected by temperature.Leakage increases with temperature because higher temperatures produce more thermally generated minority carriers.
- 24Describe the effects of PMOS and NMOS sizing in a CMOS inverter.- Larger P/N ratio means PMOS dominates and the switching point will increase
Vi -> VDD
- smaller P/N ratio means NMOS dominates and the switching point will decrease
Vi -> Gnd
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- Digital Design Fichas sobre Semiconductor Technology, creado por Bryce Reid el 17/05/2026.
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- Bryce Reid
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