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Diagrama de flujo

Tarea fundamentos de programación

Pedro José Quesada Salas Computación Español

Contenido del diagrama

  1. The CPU

  2. The CPU contains

  3. A number of registers

  4. An arithmetic logic unit

  5. The control section or control unit

  6. Connections to the memory by two buses

  7. Address side

  8. Data side

  9. Unidirectional addres bus

  10. bi-directional data bus

  11. Internal buses or data pathways

  12. Allow the output of one register to connect to the input of another

  13. The CPU registers

  14. Memory address register

    (MAR)

  15. Stores the address to access the memory. Connects the PC with the memory

  16. Memory buffer register

    (MBR)

  17. Stores information that is being sent to, or receive from the memory along the bi-directional data bus, conects the AC with the memory

  18. Accumulator

    (AC)

  19. Stores data that is being worked on by the ALU, is the key register in the data section of the CPU. Needs the MBR to connect to the memory

  20. Program counter

    (PC)

  21. Hold the address in memory of the next program instruction. Needs the MAR to be connected to the memory

  22. Instruction register

    (IR)

  23. Receive instructions form the data

    Has 2 parts

  24. IR (opcode)

  25. Takes the most important bits (data) of the instruction, tells the CPU what to do. Gets decoded and executed by the control unit, CU

  26. IR (address)

  27. Takes the least important data (bits) of the instruction for later use in the MAR. They usually forms all or part form a address

  28. Stack pointer

    (SP)

  29. Is used to hold the address of a special chunk of main memory used for temporary storage during the program execution. Is connected to the internal address bus

  30. All registers

  31. Are edge-triggered-D-types.

    The register comproimise more than a row of D-type latches which share a common clock input providing temporary storage on the CPU

  32. Units in the CPU

  33. Control Unit

    (CU)

  34. Is responsible for the timing and execution of the various register transfers required to fulfill an instruction held in the IR. It has a number of control lines coming out of it, which transmit CSL and CSP levels and pulses to the various registers and logic units

  35. Arithmetic logic unit

    (ALU)

  36. Is responsible for bit operations on data held in the AC and MBR and for storing the results. It contains arithmetic adders. Is closely asociated with the SR

  37. Status Register

    (SR)

  38. It is a collection of 1 bit flags that indicate the outcome of opeartions that the ALU has just carried out.

    These are monitored by the CU

  39. Carry "words" of information which are many bits wide, on diagrams the bus is indicated by a wide line or by a single line with a dash, usually is showed their width in bits.

    The width has increased over time

  40. Buses

  41. Microcontroller

  42. Has data bus widts of 4-bits, 8-bits, 18-bits, 32-bits and 64-bits (used by advanced computers: 64-bits)

  43. Address

  44. Is an space where conects the data.

    The formula to now how many locations an adress have via bits: 2^n (n: address lines)

  45. Main memory

  46. It will comprise mostly random access memory (RAM) with some additional read-only memory (ROM) to help the machine to start up. The main memory does not reside in the CPU but sits on the mother-board and is connected to the CPU via 2 buses (the address bus works with 24 bits and the data bus is 16 bits wide).

  47. To write or read, from memory the register transfers are written as:

  48. MBR<---[MAR] read from memory

    [MAR]<----MBR write to memory

    The MAR says where is the memory

  49. The CPU reapetedly does

  50. FETCH the next instruction from memory into the instruction register

  51. DECODE the instruction

  52. EXECUTE the instruction

Información

Descripción
Computación Diagrama sobre Tarea fundamentos de programación, creado por Pedro José Quesada Salas el 17/02/2019.
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