Processor Fundamentals

Processor Fundamentals

1. Von Neumann Machine

   • Data and programs are indistinguishable
   • Uses a single processor
   • Uses registers to follow a linear fetch-decode-execute cycle
   • Architecture of VN Machines - 3 parts
     • Inputs and Outputs
       • Cannot be connected directly to the processor
         • Connects and communicates with the processor via an I/O Controller, which has
           • An interface
           • Set of instructions and SRs
           • I/O ports
             • Allow different types of devices to connect to the CPU without needing specialised hardware, e.g. USB ports or earphone jacks
     • Processor
       • Clock
         • Timing hardware that sends out signals that synchronises the flow of data for the fetch-decode-execute cycle.
       • ALU
         • Part of the processor that does arithmetic and logical calculations. The accumulator is here
       • Control Unit
         • The section of the processor that sends signal to fetch and send data
     • Memory

2. Registers

   • PC
     • Keeps track of the address for the next instruction
     • Incremented after every fetch cycle
   • MAR
     • Temporarily stores the address that is copied to from the PC
   • MDR
     • Temporarily stores the instructions copied from the memory
   • IR
     • Holds the index value for operand modification during indirect access
   • CIR
     • Holds instructions that are about to be executed
   • ACC
     • Holds the values for arithmetic and logical calculations
   • General Registers
     • Temporarily stores any kind of data
   • Little chips placed near processor with fast access time to store temporary data
   • SR
     • Holds results of comparisons, arithmetic calculations and errors
   • Interrupt Register
     • Holds data of any incoming registers

3. RTN

   • Arrows show where the address/instruction is being copied/loaded to
   • Single square bracket denotes the contents of the register that's being transferred
   • Double brackets mean the contents of that register is logically processed before copied

4. Interrupts

   • Signal from a device or other source looking for processor attention
   • Interrupts are checked by looking at the Interrupt Register before every FDE cycle
   • Has different priority levels
   • Uses an ISR (Interrupt Service Routine) to manage Interrupts
     • If interrupt is of high priority, then
       • Contents of all registers are backed-up in a stack
         • Looks at Interrupt Source
           • Low priority then disabled, high priority ones are dealt with by copying the address of their source to the ISR
             • ISR executed
               • Registers restored
                 • Cycle repeats

5. Fetch Execute Cycle

   • Fetch
     • 1. PC address copied to MAR
     • 2. CU sends signal to MAR to collect that address and sends a signal to that address in the memory to retrieve instrucitons
       • PC is incremented
     • 3. Instructions loaded into MDR and copied into CIR
   • Decode
     • 1.CU looks at instruction in CIR
       • If addressing in CIR is direct then CU sends signal to that address and retrieves the data
       • If this instruction has indirect addressing then refers to IR and then goes to the new address
     • 2. Retrieves data from the instruction's address
     • 3. Decodes it by looking at the instruction set
   • Execute
     • Load new address operand into PC if decoding result is a jump instruction
     • If not a jump instruction, then execute it.

6. Addressing

   • Indirect
     • Addressing that tells the processor to use an address inside another address
   • Index
     • The final address is the operand address plus the Index Value
   • Relative
     • The final address is x address away from the current address in PC
   • Immediate
     • Loads a value directly into accumular
   • Direct
     • The operand is the address to retrieve the value from

7. Assembly Language, Instruction Set and Machine code

   • Instruction Set
     • Load data
       • LDD
         • LDX
           • LDI
             • LDM
               • Loads a number directly into the ACC
             • Loads contents of Address B which is stored in Address A into the ACC
           • Loads the contents from the (Operand address + Index Value) address into the ACC
         • Loads data directly from an address to the ACC
     • Data Movemnt
       • STO
         • Stores the ACC's value into an address of the Operand
     • Comparison Making
       • CMP
         • Compares ACC contents with Operand address or a number
     • Conditional Jumps
       • JPE
         • Jump to <address> if condition is true
         • JPN
           • Jump to <address> if condition is false
       • Unconditional Jump
         • JMP
           • Jump to <address> without any IF restraints
     • Input and Output
       • INP
         • Inputs a value into ACC as ASCII
         • OUT
           • Outputs a value from ACC

8. Processing Speed

   • Bus width
     • Capacity of bus - maximum bits per second transfer rate
   • Number of processors
     • The more processors there are, the more cycles can be performed at a time
   • Clock Speed
     • RPMs dictate Fetch-Execute cycles' speed