Mapa mental
Chapter 8: Memory Management
Contenido del mapa
Chapter 8: Memory Management
Background
- stall
- Cache
- Registers
- Base
- Limit
- Hardware Address Protection
- Address Binding
- Binding of Instructions
- Compile time
- Load time
- Execution time
- Address Space
- Logical address
- Logical address space
- Physical address
- Physical address space
- Logical address
- Memory-Management Unit (MMU)
- relocation register
- Linking
- Dynamic
- Static
- stub
- stub
- shared libraries
Swapping
- Backing store
- Roll out
- roll in
- Context Switch Time
- double buffering
- Swapping on Mobile Systems
Contiguous Memory Allocation
- partitions
- Resident operating system
- User processes
- Multiple-partition allocation
- Variable-partition
- Hole
- Dynamic Storage-Allocation Problem
- First-fit:
- Best-fit:
- Worst-fit
- partitions
Segmentation
- Segment table
- base
- limit
- Segment-table base register (STBR)
- Segment-table length register (STLR)
- Segment table
Paging
- frames
- page table
- Implementation of Page Table
- Page-table base register (PTBR)
- Page-table length register (PTLR)
- translation look-aside buffers (TLBs
- Structure of the Page Table
- Hierarchical Page Tables
- Two-Level Paging
- Address-Translation Scheme
- Three-level Paging Scheme
- Two-Level Paging
- Hashed Page Tables
- Inverted Page Table
- Hierarchical Page Tables
- Implementation of Page Table
- page
- Page number (p)
- Page offset (d)
- Paging Hardware
- Associative Memory
- Memory Protection
- Valid-invalid
- Shared Pages
- Shared code
- Private code and data
Structure of the Page Table
Example: The Intel 32 and 64-bit Architectures
Example: ARM Architecture
Fragmentation
- External
- compaction
- Internal
- External
Información
- Descripción
- Mapa Mental sobre Chapter 8: Memory Management, creado por m.jaber el 18/04/2016.
- Creado por
- m.jaber
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