¡GoConqr estrena diseño! Cuéntanos qué te parece.

Mapa mental

Chapter 5 Bus System

siew jiang lee Inglés

Contenido del mapa

Chapter 5 Bus System

  1. Bus Hierarchy

    • The Process Bus(System Bus)
      • The cache Bus(Backside Bus)
        • The memory Bus
          • The Local I/O Bus(High-speed I/O Bus
            • The standard I/O Bus
  2. Characteristics of Bus

    • Bus width
      • Bus speed
        • Bus Bandwidth
  3. Operation of the Bus

    • If one module wishes to send data to another
      • If the module wishes to request data from another module
  4. Control Bus

    • used to control the access & the use of the data
      • control signals transmit both command & timing information
  5. Address Bus

    • used to designate the source/destination of the data on the data bus
      • Also used to address I/O ports
        • Width determine the maximum possible memory capacity
  6. Internal Bus

    • A bus located strictly within a CPU chip for communication
  7. External Bus

    • supported by third-party hardware & software
  8. Peripheral Component Interconnect (PCI)

    • processor independent bus that can function as a performance for high speed I/O
      • System performance for high speed I/O subsystem
  9. Bus Interconnection

    • A communicate pathway connecting 1/more devices
      • Signal transmitted by any 1 devices are available for reception by all other devices
        • Typically consists of multiple communication lines
          • System bus-connect major computer component

Información

Descripción
Mapa Mental sobre Chapter 5 Bus System, creado por siew jiang lee el 23/01/2018.
Creado por
siew jiang lee
Visitas
11
Valoración

Escríbenos

¿Sobre qué es tu mensaje?

¿Qué te parece el nuevo diseño?

¿Te gusta?