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Chapter 5 Bus System
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Chapter 5 Bus System
Bus Hierarchy
- The Process Bus(System Bus)
- The cache Bus(Backside Bus)
- The memory Bus
- The Local I/O Bus(High-speed I/O Bus
- The standard I/O Bus
- The Local I/O Bus(High-speed I/O Bus
- The memory Bus
- The cache Bus(Backside Bus)
- The Process Bus(System Bus)
Characteristics of Bus
- Bus width
- Bus speed
- Bus Bandwidth
- Bus speed
- Bus width
Operation of the Bus
- If one module wishes to send data to another
- If the module wishes to request data from another module
- If one module wishes to send data to another
Control Bus
- used to control the access & the use of the data
- control signals transmit both command & timing information
- used to control the access & the use of the data
Address Bus
- used to designate the source/destination of the data on the data bus
- Also used to address I/O ports
- Width determine the maximum possible memory capacity
- Also used to address I/O ports
- used to designate the source/destination of the data on the data bus
Internal Bus
- A bus located strictly within a CPU chip for communication
External Bus
- supported by third-party hardware & software
Peripheral Component Interconnect (PCI)
- processor independent bus that can function as a performance for high speed I/O
- System performance for high speed I/O subsystem
- processor independent bus that can function as a performance for high speed I/O
Bus Interconnection
- A communicate pathway connecting 1/more devices
- Signal transmitted by any 1 devices are available for reception by all other devices
- Typically consists of multiple communication lines
- System bus-connect major computer component
- Typically consists of multiple communication lines
- Signal transmitted by any 1 devices are available for reception by all other devices
- A communicate pathway connecting 1/more devices
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- Mind Map on Chapter 5 Bus System, created by siew jiang lee on 23/01/2018.
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- siew jiang lee
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