Test
PCA_Final_Exam_New_Questions
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Preguntas del test (184)
1In 32-bit addressing mode, address field is either 1 byte or?
- A4 bytes
- B2 bytes
- C6 bytes
2If a block can be placed at every location in cache, this cache is said to be?
- AFully associative
- BDirectly mapped
- CIndirectly mapped
3Information when is written in cache, both to block in cache and block present in lower-level memory, refers to?
- AWrite-through
- BWrite-back
- CMiss rate
4Average access time of memory for having memory-hierarchy performance is given as?
- AAverage memory access time = Hit time - Miss rate
- BAverage memory access time = Hit time + (miss rate and miss penalty)
- CAverage memory access time = Hit time + Miss rate - Miss penalty
5As segment or a page is normally used for block, page-fault and address-fault is used for:
- AHit
- BMiss
- CCache
- DStack
6Virtual memory producing virtual-addresses, are translated by:
- ALogical addresses
- BPhysical addresses
- CLocal addresses
- DAll above
7Per memory reference, miss-rate can be turned into per instruction misses rate by
- AMiss rate= Memory accesses* instructions
- BMiss rate= Memory accesses/ instructions
- CMiss rate= Memory accesses-instructions
- DMiss rate= Memory accesses+ instructions
8Cutting of physical-memory into form of blocks and allocating them to different processes, stated technique is known as
- ARead back
- BCache miss
- CVirtual memory
- DCache hit
9For reducing frequency on replacement of write-back blocks, commonly used feature, is known as:
- AHit miss
- BIndex field
- CDirty bit
- DWrite-through
10If cache is not able for containing all blocks needed while execution, miss is then known as
- AHit miss
- BCache hit
- CCache miss (capacity miss)
- DHit rate
11For completing programmer's desire for unlimited quick memory, suggested economical solution was:
- AMemory hierarchy
- BTemporal locality
- CSpatial locality
12An instruction that does no operation for changing state is known as
- ANope
- BNo
- CNOP
13Set of instructions examined as candidates for potential execution is called the
- AFrame
- BCube
- CWindow
14Term 'computer architecture' is sometimes referred only to:
- AInstruction set design
- BCircuit design
- CHardware design
15General categories of instructions' operation are
- AData transfer
- BArithmetic logical
- Cfloating point
- DAll above
16The effectiveness of the cache memory is based on the property of:
- ALocality of reference
- BMemory localization
- CMemory size
17The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called _______.
- ALevel 2 cache
- BLevel 1 cache
- CRegisters
18The last on the hierarchy scale of memory devices is ______.
- AMain memory
- BBranch
- CSecondary memory
19A common measure of performance is
- APrice/performance ratio.
- BPerformance/price ratio
- COperation/price ratio.
20The number successful accesses to memory stated as a fraction is called as _____
- AMiss rate
- BHit rate
- CAccess rate
21With respect to changing among states of accomplishment and interruption, a measure of continuous service-accomplishment, is known as:
- AScalability
- BModule availability
- CModule reliability
22From a reference initial instant, a measure of service accomplishment, is known as:
- AModule reliability
- BHardware
- CSector
23To initialize any port as an output port what value is to be given to it?
- A0xFF
- B0x00
- C0x01
- DA port is by default an output port
24In AVR, which registers are there for the I/O programming of ports?
- Aall above
- BPORT
- CPIN
- DDDR
25The data will not go from the port registers to the pin unless:
- ADDR register of that port is set to 0
- BDDR register of that port is set to 1
- CPORT register of that port is set to 0
26What is the file extension that is loaded in a micro controller for executing any instruction?
- A.doc
- B.hex
- C.txt
27What type of coherence misses is - that arise from the communication of data through the cache coherence mechanism?
- ATrue sharing misses
- BFalse sharing misses
28What type of coherence misses is - that arises from the use of an invalidation based coherence algorithm with a single valid bit per cache block?:
- AFalse sharing misses
- BTrue sharing misses
29At Directory-Based Cache Coherence Protocols: The Basics, which state in the following called “Shared” in a simple protocol?
- AOne or more processors have the block cached, and the value in memory is up to date
- BExactly one processor has a copy of the cache block, and it has written the block, so the memory copy is out of date
- CNo processor has a copy of the cache block
30At Directory-Based Cache Coherence Protocols: The Basics, which state in the following called “Modified” in a simple protocol?
- ANo processor has a copy of the cache block
- BExactly one processor has a copy of the cache block, and it has written the block, so the memory copy is out of date
- COne or more processors have the block cached, and the value in memory is up to date
31At Directory-Based Cache Coherence Protocols: The Basics, which state in the following called “Uncached” in a simple protocol?
- ANo processor has a copy of the cache block
- BExactly one processor has a copy of the cache block, and it has written the block, so the memory copy is out of date
- COne or more processors have the block cached, and the value in memory is up to date
32In Non-Blocking Caches what does mean “Early restart”?
- AFetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
- BRequest the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
33What occurs at Instruction fetches when we speak about Common And Predictable Memory Reference Patterns?
- An loop iterations
- Bsubroutine call
- Cvector access
34What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns?
- Asubroutine call
- Bn loop iterations
- Cvector access
35What occurs at Data access when we speak about Common And Predictable Memory Reference Patterns?
- Asubroutine call
- Bn loop iterations
- Cvector access
36What is kernel process?
- AProvide at least two modes, indicating whether the running process is a user process or an operating system process
- BProvide at least five modes, indicating whether the running process is a user process or an operating system process
- CProvide a portion of the processor state that a user process can use but not write
- DNone of them
37Which one is NOT concerning to pitfall?
- APredicting cache performance of one program from another
- BSimulating enough instructions to get accurate performance measures of the memory hierarchy
- CImplementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
- DOver emphasizing memory bandwidth in DRAMs
38Which one is concerning to fallacy?
- APredicting cache performance of one program from another
- BSimulating enough instructions to get accurate performance measures of the memory hierarchy
- CImplementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
- DOver emphasizing memory bandwidth in DRAMs
39At VLIW Speculative Execution, which of this solution is true about problem:
Branches restrict compiler code motion?- ASpeculative operations that don’t cause exceptions
- BHardware to check pointer hazards
40At VLIW Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
- AHardware to check pointer hazards
- BSpeculative operations that don’t cause exceptions
41At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches:
- AAllow one instruction to branch multiple directions
- BSpeculative operations that don’t cause exceptions
42In Multilevel Caches “Local miss rate” equals =
- Amisses in cache / accesses to cache
- Bmisses in cache / CPU memory accesses
- Cmisses in cache / number of instructions
43In Multilevel Caches “Global miss rate” equals =
- Amisses in cache / CPU memory accesses
- Bmisses in cache / accesses to cache
- Cmisses in cache / number of instructions
44In Multilevel Caches “Misses per instruction” equals =
- Amisses in cache / number of instructions
- Bmisses in cache / accesses to cache
- Cmisses in cache / CPU memory accesses
45The time between the start and the completion of an event ,such as milliseconds for a disk access is...
- Alatency
- Bbandwidth
- Cthroughput
- Dperformance
46Total amount of work done in a given time , such as megabytes per second for disk transfer...
- Abandwidth (throughput)
- Blatency
- Cperformance
47Products that are sold by multiple vendors in large volumes and are essentially identical
- Acommodities
- Bboxes
- Cfolders
- Dfiles
48Integrated circuit processes are characterized by the:
- Afeature size
- Bpermanent size n
- Ccomplex size
- Dfixed size
49Manufacturing costs that decrease over time are ____
- Athe learning curve
- Bthe cycled line
- Cthe regular option
- Dthe final loop
50Volume is a ________ key factor in determining cost.
- Asecond
- Bfirst
- Cfifth
- Dthird
51The most companies spend only ____________ of their income on R&D, which includes all engineering.
- A4% to 12%
- B15% to 30%
- C1% to 17%
- D30% to 48%
52Desktop benchmarks divide into __ broad classes:
- Atwo
- Bthree
- Cfour
- Dfive
53A widely held rule of thumb is that a program spends __ of its execution time in only __ of the code.
- A90% 10%
- B50% 50%
- C70% 30%
- D89% 11%
54(Performance for entire task using the enhancement when possible) / (Performance for entire task without using the enhancement) is equals to:
- ASpeedup
- BEfficiency
- CProbability
- DRation
55Which of the following descriptions corresponds to static power?
- AGrows proportionally to the transistor count (whether or not the transistors are switching)
- BProportional to the product of the number of switching transistors and the switching rate Probability
- CProportional to the product of the number of switching transistors and the switching rate
- DAll of the above
56If we want to sustain four instructions per clock
- AWe must fetch more, issue more, and initiate execution on more than four instructions
- BWe must fetch less, issue more, and initiate execution on more than two instructions
- CWe must fetch more, issue less, and initiate execution on more than three instructions
- DWe must fetch more, issue more, and initiate execution on less than five instructions
57What is a hash table?
- APopular data structure for organizing a large collection of data items so that one can quickly answer questions
- BPopular data structure for updating large collections, so that one can hardly answer questions
- CPopular tables for organizing a large collection of data structure
- DPopular data structure for deletingsmall collections of data items so that one can hardly answer questions
58How this process called: “Operations execute as soon as their operands are available”
- Adata flow execution
- Binstruction execution
- Cdata control execution
- Dinstruction field execution
59For what the reorder buffer is used :
- ATo pass results among instructions that may be speculated.
- BTo pass parameters through instructions that may be speculated
- CTo get additional registers in the same way as the reservation stations
- DTo control registers
60Which one is not the major flavor of Multiple-issue processors:
- Astatistically superscalar processors
- Bdynamically scheduled superscalar processors
- Cstatically scheduled superscalar processors
- DVLIW (very long instruction word) processors
61Examples of superscalar(static):
- AMIPS and ARM
- BPentium 4, MIPS R12K, IBM, Power5
- CItanium
- DTI C6x
62Examples of superscalar(dynamic) :
- ANone at the present
- BPentium 4, MIPS R12K, IBM, Power5
- CMIPS and ARM
- DTI C6x
63Examples of VLIW processor:
- ATI C6x
- BMIPS and ARM
- CItanium
- DPentium 4, MIPS R12K, IBM, Power5
64Which is not the function of integrated instruction fetch unit:
- AInstruction memory commit
- BIntegrated branch prediction
- CInstruction prefetch
- DInstruction memory access and buffering
65In the memory hierarchy, as the speed of operation increases the memory size also increases:
- AVerdadero
- BFalso
66At VLIW by “performance and loop iteration” which time is longer?
- ALoop Unrolled
- BSoftware Pipelined
67At VLIW by “performance and loop iteration” which time is shorter?
- ASoftware Pipelined
- BLoop Unrolled
68What is a topology in interconnection networks?
- AIt indicates how the nodes a network are organised
- BIt is the minimum distance between the farthest nodes in a network
- CNumber of edges connected with a node is called node degree
69What is a Network Diameter?
- AIt is the minimum distance between the farthest nodes in a network
- BIt indicates how the nodes a network are organized
- CNumber of edges connected with a node is called node degree
70What is a Node degree?
- ANumber of edges connected with a node
- BIt indicates how the nodes a network are organized
- CIt is the minimum distance between the farthest nodes in a network
71What is a Bisection Bandwidth?
- ANumber of edges required to be cut to divide a network into two halves
- BIt indicates how the nodes a network are organized
- CIt is the minimum distance between the farthest nodes in a network
72What is Latency?
- AIt indicates how the nodes a network are organized
- BIt is the delay in transferring the message between two nodes
- CIt is the minimum distance between the farthest nodes in a network
73What is a Hardware Cost?
- AIt indicates how the nodes a network are organized
- BThe data routing functions are the functions which when executed established the path between the source and the destination
- CIt refers to the cost involved in the implementation of an interconnection network
- DIt is an indicative measure of the message carrying capacity of a network
74What is a Blocking and Non-Blocking network?
- AIt indicates how the nodes a network are organized
- BThe data routing functions are the functions which when executed establishe the path between the source and the destination
- CIn non-blocking networks the route from any free input node to any free output node can always be provided
- DIt is an indicative measure of the message carrying capacity of a network
75Design issue of interconnection network
- ASoftware Cost
- BHardware Cost
- CRLP
- DSymmetry of the network
76What is a Data transfer time?
- AIt indicates how the nodes a network are organized
- BThe data routing functions are the functions which when executed established the path between the source and the destination
- CHow long does it take for a message to reach to another processor
- DIt is an indicative measure of the message carrying capacity of a network
77Select non-blocking interconnection network
- ALinear Array
- BCube
- CCrossBar
78A modified version of the tree interconnection network
- AFat tree
- BCube
- CLinear Array
79 An interconnection network is a type of pipelined array architecture and it is designed for multidimensional flow of data
- ASystolic Array
- BCube
- CLinear Array
80A _____________ interconnection network is an extension of cube network
- AHyper Cube
- BCube
- CLinear Array
81In computer architecture, __________________ is the ability of a central processing unit (CPU) or a single core in a multi-core processor to execute multiple processes or threads concurrently, appropriately supported by the operating system.
- AMultithreading
- BComputing
- CArray processing
82Single Instruction, Single Data (SISD):
- AOnly one instruction stream is being acted on by the CPU during any one clock cycle
- BA type of parallel computer
- CCurrently, the most common type of parallel computer - most modern supercomputers fall into this category
83Pipelining …
- ABreaking a task into steps performed by different processor units, with inputs streaming through, much like an assembly line
- BA logically discrete section of computational work
- CFrom a strictly hardware point of view, describes a computer architecture where all processors have direct (usually bus based) access to common physical memory
84Shared Memory…
- AFrom a strictly hardware point of view, describes a computer architecture where all processors have direct (usually bus based) access to common physical memory
- BA logically discrete section of computational work
- CBreaking a task into steps performed by different processor units, with inputs streaming through, much like an assembly line
85What is a RISC computers?
- AReduced Instruction Set Computer
- BRational Interruptible Security Computer
- CResearch Interconnect Several Computer
86When single-processor performance improvement has dropped?
- A2003
- B2004
- C2002
87How much in percentage single-processor performance improvement has dropped to less than?
- A22%
- B11%
- C33%
88How many classes of computers classified?
- A3
- B5
- C7
89What is the PMD in computer classes?
- APercentage map device
- BPowerful markup distance
- CPeak maze development
- DPersonal mobile device
90What is the Thread Level Parallelism?
- AExploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
- BExploits parallelism among largely decoupled tasks specified by the programmer or operating system.
- CExploit data-level parallelism by applying a single instruction to a collection of data in parallel.
91What is the Request Level Parallelism:
- Ao Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
- BExploit data-level parallelism by applying a single instruction to a collection of data in parallel.
- CExploits parallelism among largely decoupled tasks specified by the programmer or operating system.
92What is the Instruction Level Parallelism:
- AExploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at medium levels using ideas like speculative execution
- BExploits parallelism among largely decoupled tasks specified by the programmer or operating system.
- CExploit data-level parallelism by applying a single instruction to a collection of data in parallel.
93What is the MISD one of the categories of computers?
- AMultiple Instructions Streams, Single Data Stream
- BMultiple Instruction Streams, Multiple Data Streams
- CMultiple Instruction Streams, Set Data Stream
94 How many elements in Trends of Technology?
- A5
- B4
- C6
95How many elements of the Instruction Set Architecture (ISA):
- A7
- B8
96How many types of dependencies do you know?
- A3
- B4
- C5
97How many possible Elements of Data Hazards?
- A3
- B6
- C8
98What is the “ISSUE” in Pipelining Basics?
- ADecode instructions, check for structural hazard
- BDecode instructions, check for data hazard
- CDecode instructions, check for control hazard
99What is the “Read Operands” in Pipelining Basics?
- AWait until no data hazards, then read operands
- BWait until no control hazards, then read operands
- CWait until no structural hazards, then read operands
100How many Optimizations’ in Cache memory Performance?
- A10
- B8
- C6
101What is the Compulsory in main categories in Cache Memory?
- Afirst-reference to a block, occur even with infinite cache
- Bcache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
- Cmisses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
102What is the Capacity in main categories in Cache Memory?
- Acache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
- Bfirst-reference to a block, occur even with infinite cache
- Cmisses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
103What is the Conflict in main categories in Cache Memory?
- Amisses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
- Bfirst-reference to a block, occur even with infinite cache
- Ccache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
104What is the Temporal Locality?
- AExploit by remembering the contents of recently accessed locations
- BExploit by fetching blocks of data around recently accessed locations
105What is the Spatial Locality?
- AExploit by fetching blocks of data around recently accessed locations
- BExploit by remembering the contents of recently accessed locations
106What is the Reducing the Hit time?
- ASmall and simple first-level caches and way-prediction
- BPipelined caches, multibanked caches, and nonblocking caches
- CCritical word first and merging write buffer
107What is the Increasing cache bandwidth?
- APipelined caches, multibanked caches, and nonblocking caches
- BSmall and simple first-level caches and way-prediction
- CCritical word first and merging write buffer
108What is the Reducing the Miss Penalty?
- ACritical word first and merging write buffer
- BSmall and simple first-level caches and way-prediction
- CPipelined caches, multibanked caches, and nonblocking caches
109What is the Reducing the Miss Rate?
- ACompiler Optimization
- BTime Optimization
- CPerformance Optimization
110Main term of dependability is SLAs?
- AService level agreements
- BStandard level achievement
- CScale level approach
111Main term of dependability is SLOs?
- AService level objectives
- BStandard level offset
112The second type of dependence is?
- AName dependence
- BData dependence
- CControl dependence
113RAW (read after write)?
- AThis hazard is the most common type and corresponds to a true data dependence
- BThis hazard corresponds to an output dependence
- CThis hazard arises from an antidependence (or name dependence)
114WAW (write after write)?
- AThis hazard corresponds to an output dependence
- BThis hazard is the most common type and corresponds to a true data dependence
- CThis hazard arises from an antidependence (or name dependence)
115WAR (write after read)?
- AThis hazard corresponds to an output dependence
- BThis hazard is the most common type and corresponds to a true data dependence
- CThis hazard arises from an antidependence (or name dependence)
116What is the element “Read Operands” in simple five-stage pipeline?
- ADecode instructions, check for structural hazards
- BWait until no data hazards, then read operands
117What is the ROB?
- AReorder buffer
- BRead only buffer
- CRelocate buffer
118How many steps in instruction execution?
- A6
- B5
- C3
- D4
119How many restrictions RAW hazards through memory are maintained?
- A2
- B3
- C4
120How many major flavors in Multiple-issue processors?
- A3
- B4
- C5
121How many functions at Integrated Instruction Fetch Units
- A3
- B4
- C5
122Speculation and the Challenge of Energy Efficiency consume excess energy in how many ways?
- A2
- B3
- C4
123The hardware model represents the assumptions made for an ideal or perfect processor is as how many follow elements?
- A5
- B4
- C6
124Infinite register renaming at The Hardware Model?
- AThere are an infinite number of virtual registers available
- BBranch prediction is perfect, all conditional branches are predicted exactly
125Perfect Branch Prediction at the Hardware Model?
- AThere are an infinite number of virtual registers available
- BBranch prediction is perfect, all conditional branches are predicted exactly
126Perfect caches at The Hardware Model?
- AAll memory accesses take one clock cycle
- BAll memory addresses are known exactly
- CAll conditional branches are predicted exactly
127Perfect memory address alias analysis at The Hardware Model?
- AAll memory addresses are known exactly
- BAll memory accesses take one clock cycle
- CAll conditional branches are predicted exactly
128Perfect jump prediction at The Hardware Model?
- AAll jumps are perfectly predicted
- BAll conditional branches are predicted exactly
- CAll memory addresses are known exactly
129What is Personal mobile device (PMD)?
- AA collection of wireless devices with multimedia user interfaces
- BA collection of computers with wireless network adapters
- CA collection of Clusters/Warehouse-scale computers
130Where the embedded microprocessors are used?
- AIn microwaves, washing machines
- BIn Personal Computers
- CIn mobile phones
131What functions has Instruction Set Architecture (ISA)?
- AServes as the boundary between the software and hardware?
- BServes as the bridge between CPU and Memory
- Co Serves as the bridge between CPU and Cache
132What is the TLP?
- ATime Level Parallelism
- BTechnology Level Parallelism
- CTask Level Parallelism
133By Moore's law, growth rate in transistor count on a chip is doubling?
- Aevery 8 to 12 months
- Bevery 12 to 16 months
- Cevery 18 to 24 months
134How should a system architect or a user think about performance, power, and energy? From the viewpoint of a system designer, how many concerns are there?
- A3
- B2
- C4
135What is the “Module reliability” in Dependability?
- AA measure of the continuous service accomplishment from a reference initial instant
- Ba measure of the service accomplishment with respect to the alternation between the two states of accomplishment and interruption.
- Ca measure of the interruption
136What is response time?
- Athe time between the start and the completion of an event
- BThe time to get an information
- CThe time spent on execution of a program
137The guiding principle of reporting performance measurements should be?
- Areproducibility
- Bresponsibility
- Ccreativity
138What is Temporal Locality?
- Arecently accessed items are likely to be accessed in the near future
- Bitems whose addresses are near one another tend to be referenced close together in time
- Cthe nearest data stored in secondary memory
139What is Spatial Locality?
- Aitems whose addresses are near one another tend to be referenced close together in time
- Brecently accessed items are likely to be accessed in the near future
- Cthe nearest data stored in secondary memory
140What is Amdahl's law?
- ADefines the speedup that can be gained by using a particular feature
- BDefines time spent on execution of a program
- CDefines data gained in one operation
141The most popular scheme is set associative, where a set is?
- Aa group of blocks
- Ba group of instructions
- Ca group of comparatives
142The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Compulsory?
- AThe very first access to a block cannot be in the cache, so the block must be brought into the cache
- BIf the cache cannot contain all the blocks needed during execution of a program
- CIf the block placement strategy is not fully associative
143The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Capacity?
- AIf the cache cannot contain all the blocks needed during execution of a program
- BThe very first access to a block cannot be in the cache, so the block must be brought into the cache
- CIf the block placement strategy is not fully associative
144The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Conflict?
- AIf the block placement strategy is not fully associative
- BThe very first access to a block cannot be in the cache, so the block must be brought into the cache
- CIf the cache cannot contain all the blocks needed during execution of a program
145The “natural” unit of organization of memory:
- AWord
- BDocument
- CSeveral Computer
146Main element of cache memory is …
- ALine
- BWord
- CString
147Typical levels of Cache memories …
- A1,2,3 levels
- B1,2,3,4,5 levels
- CCache memories have no levels
148Select internal memory …
- AHard Disk
- BCD-ROM
- CProcessor registers
149Select internal memory
- AHard Disk
- BOptical disk
- CMain memory
150Select internal memory
- ACache
- BMagnetic tape
- COptical disks
151Select external memory:
- AProcessor registers
- BCache
- CMain memory
- DHard disks
152Select external memory
- AOptical Disk
- BCache level 1
- CRegisters of processor
153Select external memory
- AMagnetic tape
- BMain memory
- CAll cache memories
154Physical types of memories:
- ADirect, Random
- BDirect, Access time
- CSemiconductor, Optical
155Physical types of memories:
- ASemiconductor, Magnetic
- BWord, Block
- CDirect, Random
156Physical types of memories:
- AMagneto-optical
- BNumber of words
- CNumber of bytes
157Select correct memory hierarchy:
- ACache – Main Memory – Secondary storages
- BSecondary storages - Cache – Main Memory
- CMain Memory – Cache - Secondary storages
158Select correct memory hierarchy:
- AProcessor registers – Cache memory – Main memory
- BCache memory – Main memory - Processor registers
- CCache memory – Processor registers - Main memory
159External, nonvolatile memory is also referred to as …
- AAuxiliary memory
- BMain memory
- CLevels of cache
160Types of cache addresses:
- ALogical, Physical
- BDirect, Associative
- CSet Associative
161A logical cache stores data using …
- Avirtual addresses
- Bvirtual addresses and physical addresses
- CPhysical addresses
162The two basic forms of semiconductor random access memory are:
- Adynamic RAM (DRAM) and static RAM (SRAM)
- Bmagnetic and optical
- CWinchester and optical disks
163Main element of cache memory?
- ATag
- BWord
- CString
164A number of chips can be grouped together to form …
- Aa memory bank
- Ba memory tags
- Ca memory lines
165Data are recorded on and later retrieved from the disk via a conducting coil named:
- AThe arm
- BThe slide
- CThe head
166The information can then be scanned at the same rate by rotating the disk at a fixed speed, known as …
- Amultiple zoned recording
- Bintersector gap
- Cthe constant angular velocity
167To increase density, modern hard disk systems use a technique known as:
- Amultiple zone recording
- Bthe constant angular velocity
168… can be removed and replaced with another disk.
- AProcessor registers
- BA non-removable disk
- CA removable disk
169For most disks, the magnetizable coating is applied to both sides of the platter, which is then referred to as ...
- Adouble sided
- Bsingle sided
- Cno sides
170The set of all the tracks in the same relative position on the platter is referred to as …
- Aa cylinder
- Ba square
- Ca circle
171On a movable head system, the time it takes to position the head at the track is known as …
- Atransfer time
- Baccess time
- Cseek time
172The operating system …
- Ais the software that controls the execution of programs on a processor and that manages the processor’s resources.
- Bis one which is understandable by us humans
- Cis a collection of Clusters/Warehouse-scale computers
- Da program that directly executes instructions written in a programming language
173The most important functions of the Operating System are:
- AThe scheduling of processes, or tasks
- BCompile C++ program codes
- CInterpret PHP program codes
- DProvide drivers for the remote devices
174The important function of the Operating System is
- AMemory management
- BProvide compiler for high level programming languages
- CIncrease size of cache
175How is the following service called? The Operating System provides a variety of facilities and services, such as editors and debuggers, to assist the programmer in creating programs…
- AProgram execution
- BAccess to I/O devices
- CProgram creation
176How is the following service called? A number of tasks need to be performed to execute a program. Instructions and data must be loaded into main memory, I/O devices and files must be initialized, and other resources must be prepared. The Operating System handles all of this for the user.
- AProgram creation
- BAccess to I/O devices
- CProgram execution
177How is the following service called? Each I/O device requires its own specific set of instructions or control signals for operation. The Operating System takes care of the details so that the programmer can think in terms of simple reads and writes.
- AAccess to I/O devices
- BProgram execution
- CProgram creation
178How is the following service called? In the case of a shared or public system, the Operating System controls access to the system as a whole and to specific system resources.
- AControlled access to files
- BAccess to I/O devices
- CSystem access
179How is the following service called? These are internal and external hardware errors, such as a memory error, or a device failure or malfunction; and various software errors, such as arithmetic overflow, attempt to access forbidden memory location, and inability of the OS to grant the request of an application. In each case, the Operating System must make the response that clears the error condition with the least impact on running applications.
- AError detection and response
- BSystem access
- CControlled access to files
180How is the following service called? A good Operating System collects usage statistics for various resources and monitor performance parameters such as response time. On any system, this information is useful in anticipating the need for future enhancements and in tuning the system to improve performance.
- AAccounting
- BSystem access
- CControlled access to files
181Select two independent dimensions of the Operating System:
- Abatch and interactive
- Bbatch and computer operator
- CInteractive and computer operator
182Select the ARM Memory-Management Parameter according to this description. These bits control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, a Permission Fault is raised.
- AAccess Permission (AP), Access Permission Extension (APX)
- BBufferable (B) bit
- CCacheable (C) bit
183Select ARM Memory-Management Parameter according to this description. Determines, with the TEX bits, how the write buffer is used for cacheable memory.
- ABufferable (B) bit
- BCacheable (C) bit
- CType Extension (TEX)
184Different types of parallelism in applications like:
- AData-level Parallelism
- BTask-level Parallelism
- CInstruction-level Parallelism
- DAll of the above
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