Test
Csa2
Crea una cuenta gratis para terminar este test
Guarda tu progreso y consulta tu resultado final.
¿Ya tienes cuenta? Inicia sesión
Preguntas del test (76)
16. How many parts of Memory Hierarchy?
- A5
- B4
- C2
- D3
27. In Memory Hierarchy, at the Outboard storage which of the following are included:
- A• Cache
- B• Main memory
- C• Magnetic tape
- D• Magnetic disk
38. In Memory Hierarchy, at the Off-line storage which of the following are included:
- A• Cache
- B• Magnetic disk
- C• Magnetic tape
- D• Main memory
49. In Memory Hierarchy, at the Inboard storage which of the following are included:
- A• Main memory
- B• Magnetic disk
- C• Magnetic tape
- D• Optical disk
510. Cache Design has these properties?
- A• Size, block size, mapping function, replacement algorithm, write policy
- B• Size, search function, write function, read policy, vector algorithm
- C• Size, mapping algorithm, vector function, write policy, replacement function
- D• Size, blocking algorithm, search function, replacement vector, read policy
611. Three techniques are possible for I/O operations:
- A• Programmed I/O, Interrupt-driven I/O, Direct memory access(DMA)
- B• Object-oriented I/O, Design I/O, Usable I/O
- C• Machine I/O, Architecture I/O, Hardware I/O
- D• Control I/O, Status I/O, Transfer I/O
712. How many principles has Deadlock?
- A3
- B5
- C4
- D6
813. Which of the following principles has Deadlock?
- A• Prevention, Avoidance, Detection
- B• Execution, Association, Starvation
- C• Exclusion, Avoidance, Starvation
- D• Starvation, Detection, Exclusion
914. Much of the work in security and protection as it relates to operating systems can be roughly grouped into four categories?
- A• Availability, confidentiality, data integrity, authenticity
- B• Safety, accountability, reliability, density
- C• Usability, integrity, confidentiality, reliability
- D• Flexibility, availability, accountability, authenticity
1015. The central themes of operating system design are all concerned with the management of processes and threads?
- A• Multiprogramming, multiprocessing, distributed processing
- B• Multitasking, multiprogramming, multithreading
- C• Multiprocessing, uniprocessing, multitasking
- D• Multithreading, distributed processing, uniprocessing
1116. Can you solve the Dining Philosophers’ Problem using monitors?
- A• Yes
- B• No
- C• Yes, but only if there are less than five philosophers
- D• No, unless there are more than five philosophers
1217. Assembly line operation is also called as?
- A• Superscalar operation
- B• Pipelining process
- C• Von Neumann cycle
- D• None of the mentioned
1318. The CISC stands for?
- A• Computer Instruction Set Compliment
- B• Complete Instruction Set Compliment
- C• Computer Indexed Set Components
- D• Complex Instruction Set Computer
1419. The secondary effect that results from instruction scheduling in large code segments is called ___?
- A• Aggressive instruction
- B• Correlating predictors
- C• Register predictors
- D• Register pressure
1520. How many instructions can be implemented in MIPS?
- A• 2 clock cycles
- B• 3 clock cycles
- C• 4 clock cycles
- D• 5 clock cycles???
1621. What do you call the given statement as “The number successful accesses to memory stated as a fraction.”
- A• Hit rate
- B• Miss rate
- C• Success rate
- D• Access rate
1722. Of the following, identify the memory usually written by the manufacturer.
- A• RAM
- B• DRAM
- C• SRAM
- D• ROM
- E• Cache Memory
1823. The Sun micro systems processors usually follow ___ architecture.
- A• CISC
- B• ISA
- C• ULTRA SPARC
- D• RISC
1924. The iconic feature of the RISC machine among the following are
- A• Reduced number of addressing modes
- B• Increased memory size
- C• Having a branch delay slot
- D• All of the above
2025. Pipe-lining is a unique feature of ___.
- A• RISC
- B• CISC
- C• ISA
- D• IANA
2126. Performance of a machine is determined by:
- A• Instruction count, Clock cycle time, Clock cycle per instruction
- B• Instruction count, Clock cycle time, Correlating predictors
- C• Clock cycle time, Correlating predictors, Aggressive instruction
- D• Clock cycle time, Clock cycles per instruction, Correlating Predictors
2227. What do you call the given statement as for type of memory?: “High density, low power, cheap, slow, need to be “refreshed” regularly”
- A• SRAM
- B• DRAM
- C• RAM
2328. Definition of Block:
- A• minimum unit that is presented or not present
- B• location of block in memory
- C• percentage of item not found in upper level
- D• memory closer to processor
- E• time to access upper level
2429. Definition of Block address:
- A• minimum unit that is presented or not present
- B• location of block in memory
- C• percentage of item not found in upper level
- D• memory closer to processor
- E• time to access upper level
25What is the total number of writes that hit in the cache?
- A• 588
- B• 784
- C• 12.5%
- D• 0.25%
2661. What is a RISC computers?
- A• Rational Interruptible Security Computer
- B• Research Interconnect Several Computer
- C• Reduced Instruction Set Computer
2762. When single-processor performance improvement has dropped?
- A• 2003
- B• 2002
- C• 2004
2863. How much in percentage single-processor performance improvement has dropped to less than?
- A• 33%
- B• 22%
- C• 11%
2964. What is the RLP?
- A• Research Level Parallelism
- B• Request Level Parallelism
- C• Random Level Parallelism
3065. How many classes of computers classified?
- A7
- B3
- C5
3166. Which distance of price has Clusters/warehouse-scale computers?
- A• 100 – 100.000$
- B• 100.000 – 200.000.000$
- C• 5.000 – 10.000.000$
3267. What is the PMD in computer classes?
- A• Percentage map device
- B• Personal mobile device
- C• Peak maze development
- D• Powerful markup distance
3368. The Application of Brokerage operations how many cost of downtime per hour?
- A• 8.870.000$
- B• 7.550.000$
- C• 6.450.000$
3469. What is the Vector Architectures and Graphic Processor Units (GPUs)
- A• Exploits data-level parallelism at modest levels with computer help using ideas like pipelining and at medium levels using ideas like speculative execution
- B• Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
- C• Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
3570. What is the Thread Level Parallelism
- A• Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads
- B• Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
- C• Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
3671. What is the Request Level Parallelism
- A• Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
- B• Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads
- C• Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
3772. What is the Instruction Level Parallelism
- A• Exploits data-level parallelism at modest levels with computer help using ideas like pipelining and at medium levels using ideas like speculative execution
- B• Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
- C• Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
3873. What is the MISD one of the categories of computers?
- A• Multiple Instruction Streams, Multiple Data Streams
- B• Multiple Instruction Streams, Set Data Stream
- C• Multiple Instructions Streams, Single Data Stream
3974. How many elements of the Instruction Set Architecture (ISA)
- A8
- B6
- C7
4075. How many issue queue used in Centralized Superscalar 2 and Exceptions
- A4
- B3
- C2
- D1
4176. How many issue queue used in Distributed Superscalar 2 and Exceptions
- A1
- B2
- C3
- D4
4277. How many instructions used in Distributed Superscalar 2 and Exceptions
- A1
- B2
- C3
- D4
4378. How many issue queue used in Centralized Superscalar 2 and Exceptions
- A1
- B2
- C3
- D4
4479. Which of the following formula is true about Issue Queue for “Instruction Ready”:
- A• Instruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no structural hazards
- B• Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc1)&& no structural hazards
- C• Instruction Ready = (!Vsrc0 || !Psrc1)&&(!Vsrc1 || !Psrc0)&& no structural hazards
- D• Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc0)&& no structural hazards
4580. What is a ARF?
- A• Architectural Register File
- B• Architecture Relocation File
- C• Architecture Reload File
- D• Architectural Read File
4681. What is a ROB?
- A• Reorder Buffer
- B• Read Only Buffer
- C• Reload Buffer
- D• Recall Buffer
4781. What is a ROB?
- A• Read Only Buffer
- B• Reorder Buffer
- C• Reload Buffer
- D• Recall Buffer
4882. What is a FSB?
- A• Finished Store Buffer
- B• Finished Stack Buffer
- C• Finished Stall Buffer
- D• Finished Star Buffer
4983. What is a PRF?
- A• Physical Register File
- B• Pending Register File
- C• Pipeline Register File
- D• Pure Register File
5084. What is a SB?
- A• Scoreboard
- B• Scorebased
- C• Scalebit
- D• Scaleboard
5185. How many stages used in Superscalar (Pipeline)?
- A5
- B4
- C6
- D7
5286. What is about Superscalar means “F-D-X-M-W”?
- A• Fetch, Decode, Execute, Memory, Writeback
- B• Fetch, Decode, Instruct, Map, Write
- C• Fetch, Decode, Excite, Memory, Write
- D• Fetch, Decode, Except, Map, Writeback
5387. Speculating on Exceptions “Prediction mechanism” is
- A• Exceptions are rare, so simply predicting no exceptions is very accurate
- B• Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
- C• Only write architectural state at commit point, so can throw away partially executed instructions after exception
- D• None of them
5488. Speculating on Exceptions “Check prediction mechanism” is
- A• Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
- B• Exceptions are rare, so simply predicting no exceptions is very accurate
- C• The way in which an object is accessed by a subject
- D• None of them
5589. What is a RT?
- A• Rename Table
- B• Recall Table
- C• Relocate Table
- D• Remove Table
5691. What is an IQ?
- A• Issue Queue
- B• Internal Queue
- C• Interrupt Queue
- D• Instruction Queue
5792. At VLIW “Superscalar Control Logic Scaling” which parameters are used?
- A• Width and Lifetime
- B• Width and Height
- C• Time and Cycle
- D• Length and Addition
5893. Out-of-Order Control Complexity MIPS R10000 which element is in Control Logic?
- A• Register name
- B• Instruction cache
- C• Data tags
- D• Data cache
5994. Out-of-Order Control Complexity MIPS R10000 which element is not in Control Logic?
- A• Integer Datapath
- B• CLK
- C• Free List
- D• Address Queue
6094. Out-of-Order Control Complexity MIPS R10000 which element is not in Control Logic?
- A• Integer Datapath
- B• CLK
- C• Free List
- D• Address Queue
6195. What is “VLIW”?
- A• Very Long Instruction Word
- B• Very Less Interpreter Word
- C• Very Light Internal Word
- D• Very Low Invalid Word
6296. At VLIW by “performance and loop iteration” which time is longer?
- A• Loop Unrolled
- B• Software Pipelined
6397. At VLIW by “performance and loop iteration” which time is shorter?
- A• Software Pipelined
- B• Loop Unrolled
6498. At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion?
- A• Speculative operations that don’t cause exceptions
- B• Hardware to check pointer hazards
65101. At VLIW Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
- A• Hardware to check pointer hazards
- B• Speculative operations that don’t cause exceptions
66102. What is an ALAT?
- A• Advanced Load Address Table
- B• Allocated Link Address Table
- C• Allowing List Address Table
- D• Addition Long Accessibility Table
67103. What is a Compulsory?
- A• first-reference to a block, occur even with infinite cache
- B• cache is too small to hold all data needed by program, occur even under perfect replacement policy
- C• misses that occur because of collisions due to less than full associativity
68104. What is a Capacity?
- A• cache is too small to hold all data needed by program, occur even under perfect replacement policy
- B• first-reference to a block, occur even with infinite cache
- C• misses that occur because of collisions due to less than full associativity
69123. What does D stand for in a D flip-flop?
- A• Direct
- B• Don’t care
- C• Data
- D• Device
- E• Disk
70124. CACHE memory is implemented using ___.
- A• Dynamic RAM
- B• Static RAM
- C• EA RAM
- D• ED RAM
71125. Stack is a ___list.
- A• FIFO
- B• LIFO
- C• FILO
- D• OFLI
- E• LFIO
72126. The computer architecture having stored program is ___.
- A• Harvard
- B• Von Neumann
- C• Pascal
- D• Ada
- E• Cobol
73127. The key technology used in IV generation computers is ___.
- A• MSI
- B• SSI
- C• LSI & VLSI
- D• Transistors
- E• Vacuum Tubes
74128. The digital circuit that generates the arithmetic sum of two binary numbers of any length is ___.
- A• Binary Adder
- B• Full Adder
- C• Half Adder
- D• Adder
- E• OR gate
75129. Which one of the following is a memory whose duty is to store most frequently used data?
- A• Main memory
- B• Cache
- C• ROM
- D• Auxiliary memory
- E• PROM
76130. How many bytes equals Petabyte (PB)?
- A• Quadrillion
- B• Million
- C• Trillion
- D• Billion
- E• 1000
Información
- Descripción
- Test sobre Csa2, creado por Nurbol Nazarov el 17/12/2018.
- Autor
- Nurbol Nazarov
- Idioma
- English
- Visitas
- 1
- Valoración
- Aún sin valoraciones Valora este test