Christmas Gift

1. 1Operations performed by a processor, such as fetching an instruction, decoding the instruction, performing an arithmetic operation, and so on, are governed by:

   1. Asystem clock
   2. Bsystem processor
   3. Cclock processor
   4. Dprocessor
   5. Eclock
2. 2Typically all operations performed by a processor begin with the:

   1. Apulse of the clock
   2. Bpulse of the processor
   3. Cit begins by itself
   4. Dboth of clock and processor pulse
   5. Enone of the above
3. 3The time between pulses called?

   1. Aclock speed
   2. Bclock rate
   3. Ccycle time
   4. Dclock cycle
   5. Ecycle rate
4. 4Typically, clock signals are generated by a ______, which generates a constant signal wave while power is applied.

   1. Aquartz crystal
   2. Bcalcium crystal
   3. Czinc crysta
   4. Dmercury crystal
   5. Eradium crystal
5. 5A processor is driven by a clock with a constant frequency f or, equivalently, a constant cycle time t, where t = 1/f:

   1. AInstruction execution rate
   2. BInstruction execution cycle
   3. CInstruction execution time
   4. DInstruction execution period
   5. ENone of the above
6. 6Average cycles per instruction of a program called:

   1. ACPU
   2. BClock cycle time
   3. CCPI
   4. DClock rate
   5. ECPE
7. 7________ is a collection of programs, defined in a high-level language, that together attempt to provide a representative test of a computer in a particular application or system programming area.

   1. AA benchmark suite
   2. BA performance suite
   3. CA IDE suite
   4. DA MIPS suite
   5. ENone of the above
8. 8Measures such as MIPS and MFLOPS have proven adequate to evaluating the performance of processors.

   1. AVerdadero
   2. BFalso
9. 9SPEC Benchmarks, which evaluates the performance of World Wide Web (WWW) servers:

   1. ASPECjvm98
   2. BSPECjbb2000
   3. CSPECweb99
   4. DSPECmail2001
   5. Eall of the above
10. 10SPEC Benchmarks, which intended to evaluate performance of the combined hardware and software aspects of the Java Virtual Machine (JVM) client platform:

    1. ASPECjvm98
    2. BSPECjbb2000
    3. CSPECweb99
    4. DSPECmail2001
    5. Eall of the above

11. 11SPEC Benchmarks, which for evaluating server-side Java-based electronic commerce applications:

    1. ASPECjvm98
    2. BSPECjbb2000
    3. CSPECweb99
    4. DSPECmail2001
    5. Eall of the above
12. 12SPEC Benchmarks, which designed to measure a system’s performance acting as a mail server

    1. ASPECjvm98
    2. BSPECjbb2000
    3. CSPECweb99
    4. DSPECmail2001
    5. Eall of the above
13. 13ENIAC stands for:

    1. AElectronic Numerical Integrator and Computer
    2. BElectronic Nuclear Integrator and Computer
    3. CEncapsulation Numerical Integrator and Commerce
    4. DEncapsulation Numerical Integrator and Computer
    5. EElectronic Numerical Integer and Computer
14. 14The general structure of the IAS computer:

    1. Amain memory
    2. Barithmetic and logic unit
    3. Ccontrol unit
    4. DInput/output equipment
    5. Eall of the above
15. 15Contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit

    1. AMemory buffer register (MBR)
    2. BMemory address register (MAR)
    3. CInstruction register (IR)
    4. DInstruction buffer register (IBR)
    5. EProgram counter (PC)
16. 16Specifies the address in memory of the word to be written from or read into the MBR

    1. AMemory buffer register (MBR
    2. BMemory address register (MAR)
    3. CInstruction register (IR)
    4. DInstruction buffer register (IBR)
    5. EProgram counter (PC)
17. 17Contains the 8-bit opcode instruction being executed.

    1. AMemory buffer register (MBR)
    2. BMemory address register (MAR)
    3. CInstruction register (IR)
    4. DInstruction buffer register (IBR)
    5. EProgram counter (PC)
18. 18Employed to hold temporarily the right-hand instruction from a word in memory

    1. AMemory buffer register (MBR)
    2. BMemory address register (MAR)
    3. CInstruction register (IR)
    4. DInstruction buffer register (IBR)
    5. EProgram counter (PC)
19. 19Contains the address of the next instruction pair to be fetched from memory.

    1. AMemory buffer register (MBR)
    2. BMemory address register (MAR)
    3. CInstruction register (IR)
    4. DInstruction buffer register (IBR)
    5. EProgram counter (PC)
20. 20Transistor is a solid-state device, made from silicon

    1. AVerdadero
    2. BFalso
21. 21The use of the _______ defines the second generation of computers.

    1. AVacuum tube
    2. BTransistor
    3. CSmall- and medium-scale integration
    4. DLarge-scale integration
    5. EVery-large-scale integration
22. 22The use of the _______ defines the first generation of computers.

    1. AVacuum tube
    2. BTransistor
    3. CSmall- and medium-scale integration
    4. DLarge-scale integration
    5. EVery-large-scale integration
23. 23The use of the ________ defines the third generation of computers.

    1. AVacuum tube
    2. BTransistor
    3. CSmall- and medium-scale integration
    4. DLarge-scale integration
    5. EVery-large-scale integration
24. 24The use of the _________ defines the fourth generation of computers.

    1. AVacuum tube
    2. BTransistor
    3. CSmall- and medium-scale integration
    4. DLarge-scale integration
    5. EVery-large-scale integration
25. 25The use of the _________ defines the fifth generation of computers.

    1. AVacuum tube
    2. BTransistor
    3. CSmall- and medium-scale integration
    4. DLarge-scale integration
    5. EVery-large-scale integration
26. 26Moore’s law: “The cost of a chip has remained virtually unchanged during this period of rapid growth in density. This means that the cost of computer logic and memory circuitry has increasing at a dramatic rate”

    1. AVerdadero
    2. BFalso
27. 27Moore’s law: “Because logic and memory elements are placed closer together on more densely packed chips, the electrical path length is shortened, decreasing operating speed”

    1. AVerdadero
    2. BFalso
28. 28Moore’s law: “The computer becomes smaller, making it more convenient to place in a variety of environments”

    1. AVerdadero
    2. BFalso
29. 29Moore’s law: “There is a reduction in power and cooling requirements”

    1. AVerdadero
    2. BFalso
30. 30Moore’s law: “The interconnections on the integrated circuit are much more reliable than solder connections. With less circuitry on each chip, there are fewer interchip connections”

    1. AVerdadero
    2. BFalso
31. 31When Intel was developed its 4004, it is the first chip to contain all of the components of a CPU on a single chip, later known as Microprocessor

    1. A1973
    2. B1971
    3. C1972
    4. D1970
    5. E1974
32. 32Processor can simultaneously work on multiple instructions. How this technique called?

    1. ABranch prediction
    2. BPipelining
    3. CData flow analysis
    4. DSpeculative execution
    5. ENone of the above
33. 33The processor looks ahead in the instruction code fetched from memory and predicts which branches, or groups of instructions, are likely to be processed next

    1. ABranch prediction
    2. BPipelining
    3. CData flow analysis
    4. DSpeculative execution
    5. ENone of the above
34. 34The processor analyzes which instructions are dependent on each other’s results, or data, to create an optimized schedule of instructions

    1. ABranch prediction
    2. BPipelining
    3. CData flow analysis
    4. DSpeculative execution
    5. ENone of the above
35. 35This enables the processor to keep its execution engines as busy as possible by executing instructions that are likely to be needed

    1. ABranch prediction
    2. BPipelining
    3. CData flow analysis
    4. DSpeculative execution
    5. ENone of the above
36. 36The “natural” unit of organization of memory

    1. AWord
    2. BAddressable units
    3. CUnit of transfer
    4. DSequential access
    5. EDirect access
37. 37For main memory, this is the number of bits read out of or written into memory at a time

    1. AWord
    2. BAddressable units
    3. CUnit of transfer
    4. DSequential access
    5. EDirect access
38. 38Memory is organized into units of data, called records; access must be made in a specific linear sequence

    1. AWord
    2. BAddressable units
    3. CUnit of transfer
    4. DSequential access
    5. EDirect access
39. 39For random-access memory, this is the time it takes to perform a read or write operation

    1. AAccess time
    2. BMemory cycle time
    3. CTransfer rate
    4. DPerformance
    5. EAll of the above
40. 40The L2 cache is slower and typically larger than the L1 cache, and the L3 cache is slower and typically larger than the L2 cache

    1. AVerdadero
    2. BFalso
41. 41The L2 cache is faster and typically larger than the L1 cache, and the L3 cache is slower and typically larger than the L2 cache

    1. AVerdadero
    2. BFalso
42. 42Additional hardware is used to ensure that all updates to main memory via cache are reflected in all caches

    1. ABus watching with write through
    2. BHardware transparency
    3. CNoncacheable memory
    4. DSoftware transparency
    5. ENone of the above
43. 43Each cache controller monitors the address lines to detect write operations to memory by other bus masters

    1. ABus watching with write through
    2. BHardware transparency
    3. CNoncacheable memory
    4. DSoftware transparency
    5. ENone of the above
44. 44Only a portion of main memory is shared by more than one processor, and this is designated as:

    1. ABus watching with write through
    2. BHardware transparency
    3. CNoncacheable memory
    4. DSoftware transparency
    5. ENone of the above
45. 45Larger blocks increase the number of blocks that fit into a cache; because each block fetch overwrites older cache contents, a small number of blocks results in data being overwritten shortly after they are fetched

    1. AVerdadero
    2. BFalso
46. 46A state in which data requested for processing by a component or application is found in the cache memory

    1. Acache hit
    2. Bcache miss
    3. Ccache overwrites
    4. Dcache set
    5. Ecache access time
47. 47The basic element of a semiconductor memory is:

    1. Amemory cell
    2. Bcache memory
    3. CRAM
    4. DDRAM
    5. ENone of the above
48. 48RAID stands for

    1. ARandom Access Integral Disk
    2. BRedundant Access Integral Disk
    3. CRandom Array Independent Disk
    4. DRedundant Array Independent Disk
    5. ERedundant Access Independent Disk
49. 49Data are recorded on and later retrieved from the disk via a conducting coil named the tail

    1. AVerdadero
    2. BFalso

Descripción

Test sobre Christmas Gift, creado por Daniyar Adilkhanov el 21/12/2018.

Autor

Daniyar Adilkhanov

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