Test
grasgr4awgs
Este test tiene tipos de pregunta que se abren en el reproductor de siempre.
Preguntas del test (171)
1According to the text, what are the five (5) classic components of a computer. Check all that apply.
- AInput.
- BOutput.
- CConnector cables.
- DMemory.
- EProcessor.
- FDatapath.
- GI/O Devices.
2According to the text, which of the following are considered classes of computing. Check all that apply
- ADesktops / Laptops.
- BServers.
- CSuper computers.
- DEmbeded systems.
- EYour fingers (when used for counting).
- FMobile Computing.
- GAn abacus.
3MIPS is which type of processor?
- ACISC.
- BHybrid.
- CRISC.
4Which of the following items can impact program performance?
- AAlgorithm.
- BProgramming language.
- CCompiler.
- DTime of day.
- EInstruction set architecture (ISA).
- FDocumentation.
5Which of the following is true regarding response time?
- ATime of day when program is started.
- BTotal work done in a given time.
- CTime between start and finish of a single task.
6Which of the following is true regarding throughput time?
- ATime of day when program is started.
- BTotal work done in a given time
- CTime between start and finish of a single task.
7Which of the following are performance measures? Check all that apply.
- AElapsed time.
- BResponse time.
- CHeat generated by the CPU.
- DThroughput.
8What is the range of an unsigned byte?
- A0 - 255
- B0 - 65535
- C-128 - +127
- DNone of these answers are correct.
9What is the range of a signed byte?
- A0 to 255
- B0 to 65535
- C-128 to +127
- DNone of these answers are correct.
10What is the range of a C++ short?
- A0 to 65535
- B-128 to +127
- C−32,768 to +32,767
- DNone of these answers are correct.
11What is the range of a C++ unsigned short?
- A0 to 65535
- B-127 to +128
- C−32,768 to +32,767
- DNone of these answers are correct.
12What is the range of a C++ int?
- A0 to 4,294,967,295
- B−32,768 to +32,767
- C−2,147,483,648 to +2,147,483,647
- DNone of these answers are correct.
13What is the range of a C++ unsigned int?
- A0 to 4,294,967,295
- B−32,768 to +32,767
- C−2,147,483,648 to +2,147,483,647
- DNone of these answers are correct.
14What is the hex, byte size, two's compliment representation of -7 (decimal)?
- A-0x07
- B0xf7
- C0xff
- D0xf9
15What is the hex, 16-bit (short) size, two's compliment representation of -9 (decimal)?
- A-0x0007
- B0xfff7
- C0xffff
- D0xfff9
16What is the hex, 32-bit (int) size, two's compliment representation of -9 (decimal)?
- A-0x00000009
- B0xffffffff
- C0xfffffff9
- D0xfffffff7
17What is the decimal representation of 0xFFFFFFFB (hex, double-word size, two's compliment)?
- A-11
- B11
- C-5
- D5
18What is the decimal representation of 0xC1440000? Assume IEEE 32-bit floating point format.
- A9.5
- B-4.5
- C-12.25
- D-9.5
- ENone of these answers are correct.
19What is the MIPS architecture philosophy?
- ARISC.
- BCISC.
- CGo fast no matter what.
- DNone of these answers is fully correct.
20On the MIPS architecture, what is the smallest amount of memory that can be easily accessed?
- Abit
- Bbyte
- Chalf-word
- Ddobuel-word
- Edepends on the data declaration
21On the MIPS architecture, which register (name) is used to hold the address of the stack?
- A$pc
- B$fp
- C$sp
- D$pw
- ENone of these answers is fully correct.
22On the MIPS architecture, which register (name) is used to point to the next instruction?
- A$pc
- B$fp
- C$sp
- D$psw
- ENone of these answers is fully correct.
23How much memory is used by a word size integer on the MIPS architecture.
- AOne (1) byte.
- BTwo (2) bytes.
- CThree (3) bytes.
- DFour (4) bytes.
- ENone of these answers is fully correct.
24How much memory is used by a half-word size integer on the MIPS architecture.
- AOne (1) byte.
- BTwo (2) bytes.
- CThree (3) bytes.
- DFour (4) bytes.
- ENone of these answers is fully correct.
25Which MIPS registers can be used for indirection?
- AAll registers.
- BAll integer registers.
- CDedicated indirection registers.
- DThe $t<number> registers.
- ENone of these answers is fully correct.
26What are the three operands used for on the "add" instruction?
- ARdest, Rsrc, Src
- BRsrc, Rsrc, Rdest
- CRsrc, Rsrc, Rscr
- DNone of these answers is fully correct.
- EIncorrect question, there are only two arguments.
27When there are three operands for the multiply ("mul") instruction, where is the answer placed?
- ARdest
- BRsrc
- C$psw
- Done of these answers is fully correct.
- EThe $t<number> registers.
28Can an immediate value be used in an add or subtract operation?
- AYes, only in the Src operand.
- BYes, only in the Rdest operand.
- CNo.
- DNone of these answers is fully correct.
29Given the code fragment;
li $t1, 10
li $t2, 4
li $t3, 5
add $t5, $t2, $t3
sub $t2, $t2, 1
mul $t3, $t2, $t3
div $t2, $t3, 6
What would be in the registers after execution in hex? Note, must precede hex number with 0x.
$t1 = [blank_start]0x0000000A[blank_end]
$t2 = [blank_start]0x00000002[blank_end]
$t3 = [blank_start]0x0000000F[blank_end]
$t5 = [blank_start]0x00000009[blank_end]- A0x0000000A
- B0x00000002
- C0x0000000F
- D0x00000009
30How many bits do the MIPS registers hold?
- A8 bits.
- B8 bytes.
- C32-bits.
- D64-bits.
31How many bits are used for each of the following?
byte = [blank_start]8 bits[blank_end]
half-word = [blank_start]16 bits[blank_end]
word = [blank_start]32 bits[blank_end]
double-word = [blank_start]64 bits[blank_end]- A8 bits
- B16 bits
- C32 bits
- D64 bits
32Which of the following instructions is the fastest?
lw $t0, num1
move $t1, $s3
sw $t5, num2- Alw $t0, num1
- Bmove $t1, $s3
- Csw $t5, num2
- DThey are all about the same.
33Which registers can not be used for indirection?
- AAll integer registers.
- BAll registers.
- CFloating point registers.
- DNone of these answers is fully correct.
34The MIPS architecture will only run on a simulator?
- AVerdadero
- BFalso
35What is the instruction for an unconditional branch? Check all that apply.
- Ajmp <label>
- Bb <label>
- Cj <label>
- Dbranch <label>
- ENone of these answers is fully correct.
36Given the code fragment;
li $t1, 10
li $t2, 3
move $t3, $t2
add $t3, $t3, 3
add $t5, $t2, $t3
sub $t2, $t2, 1
mul $t3, $t2, $t3
div $t2, $t3, 7
What would be in the registers after execution in hex? Note, must precede hex number with 0x
$t2 = [blank_start]0x00000002[blank_end]
$t3 = [blank_start]0x0000000C[blank_end]
$t5 = [blank_start]0x00000009[blank_end]- A0x00000002
- B0x0000000C
- C0x00000009
37Given the code fragment;
list: .word 10, 8, 6, 4, 2
la $t0, list
li $t2, 3
lp: lw $t3, ($t0)
add $t0, $t0, 4
sub $t2, $t2, 1
bnez $t2, lp
lw $t5, list
What would be in the registers after execution in hex? Note, must precede hex number with 0x.
$t2 = [blank_start]0x00000000[blank_end]
$t3 = [blank_start]0x00000006[blank_end]
$t5 = [blank_start]0x0000000A[blank_end]- A0x00000000
- B0x00000006
- C0x0000000A
38For a 32-bit value returning function, where is the return value placed?
[blank_start]$v0[blank_end]- A$v0
39Where is the return address placed for a function call?
[blank_start]$ra[blank_end]- A$ra
40For the following function call;
func(fltVal, fltAddr, fltVal, intVal)
where specifically is the
1st = [blank_start]$f12[blank_end]
2nd = [blank_start]$a1[blank_end]
3rd = [blank_start]($fp)[blank_end]
4th = [blank_start]$a3[blank_end]
argument passed? For stack based arguments, if any, respond in terms of $fp.- A$f12
- B$a1
- C($fp)
- D$a3
41Given the following code fragment;
lst2: .word 1, 3, 5, 7, 9, 11, 13, 15, 17, 19
la $s0, lst2
add $s0, $s0, 4
li $s1, 3
li $t5, 0
lp2: lw $t7, ($s0)
add $t5, $t5, $t7
sub $s1, $s1, 1
add $s0, $s0, 4
bnez $s1, lp2
lw $t3, ($s0)
What is the contents of the register after execution. Note, must precede hex number with 0x.
$t3 = [blank_start]0x00000009[blank_end]
$t5 = [blank_start]0x0000000F[blank_end]
$t7 = [blank_start]0x00000007[blank_end]- A0x00000009
- B0x0000000F
- C0x00000007
42Given the instruction;
add $t4, $t4, $t5
What is the op (operation) value?- A0b000001
- B0b100001
- C0b000010
- D0b100010
- E0b100000
- F0b000000
43Given the instruction
add $t4, $t4, $t5
What is the value for the rd (register destination).- A0b01011
- B0b01010
- C0b01111
- D0b01100
- E0b01101
44Given the instruction
add $t4, $t4, $t5
What is the value for shift amount?- A0b00000
- B0b00001
- C0b00010
- DIndeterminable for this instruction.
45Given the instruction
add $t4, $t4, $t5
What is the function value?- A0b000001
- B0b100001
- C0b000010
- D0b100010
- E0b100000
- F0b000000
46Given the instruction
add $t4, $t4, $t5
What is the opcode for this instruction (in hex, which must be proceeded with an 0x).
[blank_start]0x018D6020[blank_end]- A0x018D6020
47How is the standard calling convention implemented?
- AThe standard calling convention is optional and only implemented in large projects.
- BThe "jal" and "jr" instructions ensure implementation of the standard calling convention.
- CIt is implemented and enforced by a subset of specific instructions.
- DIt is implemented in software by programmers and in compilers.
48Which register is used for the return of 32-bit function values?
[blank_start]$v0[blank_end]- A$v0
49For the following high-level language call;
func1(num1, num2, &ans);.
Where is the num2 argument passed? Assume all arguments are C++ integers and are initialized appropriately.
[blank_start]$a1[blank_end]- A$a1
50When does the value for a load immediate instruction become too large for a single instruction?
- AWhen the value is greater than 2^14.
- BWhen the value is greater than 2^15.
- CWhen the value is greater than 2^16.
- DWhen the value is greater than 2^17.
51When the value for a load immediate instruction is too large, what is required?
- AThe instruction can not be executed.
- BThe value is reduced and the assembler will issue a warning.
- CA smaller value must be used followed by an ADD operation in order to obtain the final larger value.
- DThe instruction is implemented as two instructions.
52How does the conditional jump (e.g., beq <Rsrc>, <Src>, <label>) work?
- AIf true, the $pc is set to the address represented by <label>.
- BThe conditional jumps are replaced by pseudo instructions that use a jump instruction as required.
- CThe $pc register is alwasy set to the value of the <label>.
- DIf true, the offset calculated by the assember is added the current $pc value.
53Why is the range of a conditional jump (e.g., beq <Rsrc>, <Src>, <label>) is limited?
- AIt is not limited.
- BThe range is limited by the expected maximum size of a function.
- CThe limit helps enforce the general philosophy that smaller is better.
- DThe instruction format set limits the size of the offset in the conditional jump instruction.
54What is the range of a conditional jump (e.g., beq <Rsrc>, <Src>, <label>)?
- A± 2^14 bytes.
- B± 2^15 bytes.
- C± 2^16 bytes.
- D± 2^17 bytes.
55What is the range of an unsigned byte?
- A0 - 65535
- B0 - 255
- C-128 - +127
- DNone of these answers are correct.
56What is the hex, double-word size, two's compliment representation of -11 (decimal)?
- A-0x0000000b
- B0xfff4
- C0xfffffff4
- D0xffffffff5
57What is the decimal representation of 0xFFFFFFFD (hex, double-word size, two's compliment)?
[blank_start]-3[blank_end]- A-3
58Given the following operation;
0b00001110
+ 0b00000110
----------------------
What is the final result in hex, byte size? Recall hex numbers are preceded with a 0x.
[blank_start]0x14[blank_end]- A0x14
59Given the following operation?
0b001000111100
+ 0b010101110010
----------------------------
What is the final result in binary.
[blank_start]0b011110101110[blank_end]- A0b011110101110
60Given the following operation on a 8-bit processor;
0b00001110
+ 0b11111010
----------------------
What happens as a result in decimal?
[blank_start]8[blank_end]- A8
61How is binary subtraction performed?
- ABy negating one operand and performing addition.
- BBy performing addition and negating the final result.
- CUsing a binary borrow as needed.
- DSubtraction is a function of the CPU Arithmetic Logic Unit (ALU) which uses magic.
62For a signed integer (32-bits), how is it possible to determine the sign (+ or -)?
- ABy adding the compliement of the number to the original value and checking the final result; 0 (positive) or 1 (negative).
- BBy dividing the number by itself and checking the least significant bit for 0 (positive) or 1 (negative).
- CBy checking the least significant bit for 0 (positive) or 1 (negative).
- DBy checking the most significant bit for 0 (positive) or 1 (negative).
- ENone of these answers are fully correct.
63What is the result of the following operation?
li $t3, 9
sll $t3, $t3, 1
Answer in hex.- A0x14
- B0x11
- C0x18
- D0x12
64Given the following operation on a 4-bit processor;
1010
+ 0110
-----------
What happens as a result?- ANo result is provided.
- B0b10000
- CThis can not be done.
- DA carry is generated indicating an overflow.
65Given the following opcode, what is the instruction?
0x34080007- Ali $0, 7
- Badd $t8, $t8, 7
- Cor $t8, 7
- Dori $t8, $0, 7
66What is the decimal representation of 0xFFFFFFFA (hex, word size, two's compliment)?
[blank_start]-6[blank_end]- A-6
67What is the IEEE 32-bit representation for 0xC1930000 in decimal?
[blank_start]-18.375[blank_end]- A-18.375
68Is the MIPS architecture, as simulated by QtSpim, big-endian or little-endian?
- ABig-endian.
- BLittle-endian.
- CBoth.
- DNeither.
69There are three integer instruction formats (r-format, i-format, and j-format). Which instruction format is used for each of the following instructions?
add Rd, Rs, Immediate
[blank_start]i-format[blank_end]
beq Rs, Rt, <label>
[blank_start]i-format[blank_end]
and Rd, Rs, Rt
[blank_start]r-format[blank_end]- Ai-format
- Bi-format
- Cr-format
70Given the CPU Block Diagram (above) and the six (6) resource blocks (PC Unit, Instruction Memory Unit, Register File, ALU, Data Memory Unit, and Branch Adder Unit).
Which resource blocks perform a useful function for an
addi Rd, Rs, Immediate
instruction? Check all that apply.- APC Unit.
- BRegister File.
- CInstruction Memory Unit.
- DALU
- EData Memory Unit.
- FBranch Adder Unit.
71Given the CPU Block Diagram (above) and the six (6) resource blocks (PC Unit, Instruction Memory Unit, Register File, ALU, Data Memory Unit, and Branch Adder Unit).
Which resource blocks perform a useful function for an
sw Rt, (Rs)
instruction? Check all that apply.- APC Unit.
- BRegister File.
- Cinstruction Memory Unit.
- DALU.
- EData Memory Unit.
- FBranch Adder Unit.
72Given the CPU Block Diagram (above) and the six (6) resource blocks (PC Unit, Instruction Memory Unit, Register File, ALU, Data Memory Unit, and Branch Adder Unit).
Which resource blocks do not produce output(s) for an
addi Rd, Rs, Immediate
instruction? Check all that apply.- APC Unit.
- BRegister File.
- CInstruction Memory Unit.
- DALU.
- EData Memory Unit.
- FBranch Adder Unit.
73Given the CPU Block Diagram (above) and the six (6) resource blocks (PC Unit, Instruction Memory Unit, Register File, ALU, Data Memory Unit, and Branch Adder Unit).
Which resource blocks do produce an output but the output is not used for an
addi Rd, Rs, Immediate
instruction? Check all that apply.- APC Unit.
- BRegister File.
- CInstruction Memory Unit.
- DALU.
- EData Memory Unit.
- FBranch Adder Unit.
74What are the values of control signals generated by the control for the instruction;
addi Rd, Rs, Imm
Note, '1' is asserted (on) and '0' is not asserted (off). For ALUop, add is 0 and sub is 1.
RegWrite = [blank_start]1[blank_end]
MemRead = [blank_start]0[blank_end]
ALUMux = [blank_start]1[blank_end]
MemWrite = [blank_start]0[blank_end]
ALU Operation = [blank_start]0[blank_end]
RegMux = [blank_start]1[blank_end]
Branch = [blank_start]0[blank_end]- A1
- B0
- C1
- D0
- E0
- F1
- G0
75Which processor functional unit performs the subtraction operation?
- AProgram counter (PC).
- BArithmetic Logic Unit (ALU).
- CData Memory Unit.
- DRegister File.
- EInstruction Memory Unit.
76Which processor functional unit obtains the next instruction to be executed?
- AProgram counter (PC).
- BArithmetic Logic Unit (ALU).
- CData Memory Unit.
- DRegister File.
- EInstruction Memory Unit.
77Which functional unit determines or sets the next instruction to be executed?
- AProgram counter (PC).
- BArithmetic Logic Unit (ALU).
- CData Memory Unit.
- DRegister File.
- EInstruction Memory Unit.
78Does the Data Memory Unit provide an output for a jal <functionName> instruction?
- AYes.
- BNo.
- CYes, but only for long jump.
- DYes, when the function is not currently in memory (which will require a page fault).
79ow are all the CPU function units synchronized?
- AThey are not, each actions only when input become available.
- BA clocking methodology defines when signals can be read and when they are written.
- CEach functional unit has a built-in clock which is synchronized at boot time.
- DNone of these answers are correct.
80As defined in the text, the processor also includes a sign extend functional unit with a 16-bit input and a 32-bit output. Specifically, what happens during this step?
- AA logical right shift of 16 bits is performed.
- BAn arithmetic right shift of 16 bits is performed.
- CThe upper 16 bits are set to zero (since the value may be an address).
- DThe 16 bit input is converted to 32-bit input by copying the sign into the upper 16 bits.
81The processor has an input control signal for RegWrite. When would this signal be set to 1 (1 = on and 0 = off).
- AIt is turn on (1) for all non-memory operations and off (0) for all memory operation.
- BIt is turned on (1) for conditional branch instructions.
- CIt is turned on (1) for the store word (sw) instructions.
- DIt is turned on (1) for arithmetic instructions.
82Is it possible for a CPU functional unit to provide an output and that output be ignored?
- ANo.
- BYes, this is possible but must be eliminated to ensure maximum processor performance.
- CYes.
- DNo, such extranious outputs would cause anomolous errors.
83Where do the input signals come from for the Arithmetic Logic Unit (ALU)?
- AThe ALU control signals are determined by register values.
- BThe ALU control signals are determined by the program count value.
- CThe ALU control signals are determined by data values.
- DThe control signals are based on the op field from the instruction.
84Given the above diagram and the following instruction;
sub3 Rd, Rs, Rt, Rx where, Rd = Rs + Rt + Rx
Which existing blocks (if any) can be used for the instruction? Check all that apply.- AProgram counter (PC).
- BInstruction Memory Unit.
- CRegister File.
- DArithmetic Logic Unit (ALU).
- EData Memory Unit.
- FBranch Adder Unit.
85Given the above diagram and the following instruction;
sub3 Rd, Rs, Rt, Rx where, Rd = Rs + Rt + Rx
Can the existing 32-bit instruction format be used?- ANo, some additional bits (for the extra register) would be required.
- BThe existing r-format can be used without any changes.
- CThe extra bits required (for the extra register) make this operation impossible to implement.
- DYes, however a new format would be required.
86Given the above diagram and the following instruction;
sub3 Rd, Rs, Rt, Rx where, Rd = Rs + Rt + Rx
Which existing block or blocks (if any) would need to be updated in order to implement the instruction? Check all that apply.- AProgram counter (PC).
- BInstruction Memory Unit.
- CRegister File.
- DArithmetic Logic Unit (ALU).
- EData Memory Unit.
- FBranch Adder Unit.
87Given the above diagram and the following instruction;
sub3 Rd, Rs, Rt, Rx where, Rd = Rs + Rt + Rx
Would implementation of this instruction be considered simple or difficult?- AThis would be simple as no hardware changes would be required.
- BThis would be considered simple as it requires minimal reconfiguration of the existing functional unit.
- CYes, this would be considered difficult due to the additional function units required.
- DThis update is so difficult that it would not be possible even with a major reconfiguration.
88Given the above diagram and the following instruction;
add3 Rd, Rs, Rt, Rx where, Rd = Rs + Rt + Rx
What new signals might be required (if any) from the control unit to support this instruction? Check all that apply.- ANo new signals would be required.
- Bhe new signals required would not impact the control unit.
- CWould need a control signal that informs the new Instruction Memory Unit to perform the new instruction
- DWould need a control signal that informs the new ALU to perform the new instruction.
89Given the following instruction word and the above diagram.
0x8CC10028
What is the register value provided to the Read Register 1 input? [blank_start]0b00110[blank_end]
s the value (Read Register 1) actually read by the register file? [blank_start]Yes[blank_end]
What is the register value provided to the Read Register 2 input? [blank_start]0b00001[blank_end]
Is the value (Read Register 2) actually read by the register file? [blank_start]Yes, but it is not used.[blank_end]
What is the register value provided to the Write Register input? [blank_start]0b00001[blank_end]
Is the value (Write Register) actually read by the register file? [blank_start]Yes[blank_end]
What is the value of the RegDst control signal for this instruction? [blank_start]0[blank_end]
What is the value of the MemRead control signal for this instruction? [blank_start]1[blank_end]- A0b00110
- BYes
- C0b00001
- DYes, but it is not used.
- E0b00001
- FYes
- G0
- H1
90Given the above diagram, and the below signal fault:
Fault: Instruction Memory, output instruction, bit 6
Assume that processor testing is performed by filling the $pc, registers, data, and instruction memories with some values and letting a single instruction execute. What type of instruction would be required to test each possible fault for a “stuck-at-0” type fault?- ABit 6 is party of the op code, so an ADD instruction could be used to test.
- BBit 6 is part of the destination register, so an add instruction with bit 6 set could be used (like add $5, $4, $3) could be used.
- CBit 6 is part of the destination register, so an add instruction with bit 6 set could be used (like addi $16, $zero, 1) could be used.
- DBit 6 is part of the offset/immediate, so an add instruction would with bit 6 set (like add $1, $zero, 64) could be used.
- EBit 6 is part of the offset/immediate, so an add instruction would with bit 6 set (like add $1, $zero, 15) could be used.
- FIt is not possible to test this specific fault.
91If a processor has a 10 stage pipeline and instructions and there are no penalties associated hazards and given a program with several billion instructions, what is the speed-up of this processor for this program compared to a non-pipelined processor?
- A10 times.
- B2 times.
- Cnone.
- DInsufficient information to asnwer.
92Given a processor has a 10 stage pipeline and instructions and there are no penalties associated hazards and given a program with several billion instructions;
If the performance of the ALU is improved by 50%, what will be the impact on the overall performance of the CPU?- A10 times.
- B2 times.
- CNone.
- DInsufficient information to answer.
93Given a processor has a 10 stage pipeline and instructions and there are no penalties associated hazards and given a program with several billion instructions;
If the performance of the ALU is degraded by 50%, what will be the impact on the overall performance of the CPU?- A10 percent (1/10) worse.
- B50 percent worse.
- CNone.
- DInsufficient information to asnwer.
94A described in the text, a MIPS instructions had five (5) stages of execution. Show the order of the stages below.
Stage Number Stage
1st stage [blank_start]IF[blank_end]
2nd stage [blank_start]ID[blank_end]
3rd stage [blank_start]EX[blank_end]
4th stage [blank_start]MEM[blank_end]
5th stage [blank_start]WB[blank_end]- AIF
- BID
- CEX
- DMEM
- EWB
95At which stage is the $pc register updated?
- AIF
- BID
- CEX
- DME
- EWB
96Which of the following are considered hazards in a pipeline? Check all that apply.
- APipeline hazard.
- BData hazard.
- CArithmetic Logic Unit (ALU) hazard.
- DControl hazard.
- EData memory unit hazard.
- FStructural hazard.
- GAll of these answers are correct.
97Which of the following would be considered an appropriate mitigation for a control hazard? Check all that apply.
- AImplementation of a delayed branch.
- BNot allowing two data accesses on a instruction.
- CImplementation of static branch prediction.
- DForwarding a value that is needed before it has been written to its final location.
98The MIPS five stage pipe appears to require that a register read and a register write be performed on the same stage. Can this be done?
- ANo, this is a structural hazard.
- BOnly when there is no conflict based on the specific operations being performed.
- CNo.
- DYes.
99Does a conditional branch generate a data hazard?
- AOnly possible when the conditional branch accesses memory.
- BYes.
- CNo.
- DInsufficient information to answer.
100What is static branch prediction?
- AAdding two stalls after each conditional branch instruction.
- BFlushing the pipeline for conditional branches.
- CGuess which direction a conditional branch might go and start loading instructions.
- DNone of these answers are correct.
101Which of the following would be considered an appropriate mitigation for a data hazard? Check all that apply.
- ANot allowing two data accesses on a instruction.
- BImplementation of a delayed branch.
- CImplementation of static branch prediction.
- DForwarding a value that is needed before it has been written to its final location.
102Can the compiler or programmer re-write a series of instructions in order to eliminate a data hazard?
- ANo, this is not possible.
- BYes, theoretically this is possible but can not actually be done due to the difficulty of finding data hazards.
- CYes, this is typically done to address data hazards.
- DYes, this is possible but not typically required.
103Given the below code fragment:
and $1, $5, $7 [blank_start]No hazard.[blank_end]
and $1, $1, $5 [blank_start]Data hazard on register $1.[blank_end]
beq $6, $3, lbl2 [blank_start]Control hazard.[blank_end]
sll $4, $3, $1 [blank_start]No hazard.[blank_end]
xor $4, $3, $4 [blank_start]Data hazard on register $4.[blank_end]- AData hazard on register $4.
- BNo hazard.
- CControl hazard.
- DData hazard on register $1.
- ENo hazard.
104Given the below code fragment:
1) add $2, $3, $1
2) add $7, $6, $4
3) sw $2, 20($4)
Is there a data hazard between line 1 and line 3? Assume data forwording.- AYes.
- BYes, but only if the value in regsiter $2 is actually updated/altered in line 1.
- CYes, based on register $2.
- DNo data hazard.
105Given the below code fragment:
1) and $1, $3, $5
2) lw $2, 8($1)
3) srl $5, $6, 4
4) xor $8, $5, $2
Identify the data hazards (if any). Check all that apply.- ABetween line 1 and line 2 on register $1, stall required.
- BBetween line 1 and line 2 on register $1, forwarding required.
- CBetween line 2 and line 3 on register $5, no forwarding required.
- DBetween line 2 and line 3 on register $5, forwarding required.
- EBetween line 3 and line 4 on register $5, stall required.
- FBetween line 3 and line 4 on register $5, forwarding required.
106Given the below code fragment:
1) add $s0, $a0, $t2
2) add $t5, $s0, $t1
3) sw $v0, 4($t5)
4) and $t8, $v0, $t2
Identify the data hazards (if any). Check all that apply.- ABetween line 1 and line 2 on register $s0, no forwarding required.
- BBetween line 1 and line 2 on register $s0, forwarding required.
- CBetween line 2 and line 3 on register $t5, forwarding required.
- DBetween line 2 and line 3 on register $t5, no forwarding required.
- EBetween line 3 and line 4 on register $v0, forwarding required.
107Which memory technology is the fastest but most expensive?
- ASDRAM
- BDDR SDRAM
- CSRAM
- DDRAM
- EFRAM
108in the hierarchy of memories, the [BLANK] memory is the closesest to the processor.
- ASlowest.
- BLargest.
- CFastest.
- DNone of the above.
109When an memory access occurs and the memory location is in cache; this is called a:
- Ahit
- Bmiss
- Ctry
- DNone of the above.
110When an memory access occurs and the memory location is not in cache; this is called a:
- AHit
- BMiss
- CTry
- DNone of the above
111Which of the following would be considers an appropriate mitigation for a structural hazard? Check all that apply.
- AForwarding a value that is needed before is has been written to its final location
- BImplementation of a delayed branch
- CNot allowing two data access on an instruction
- DImplementation o f a static branch
- EUse of multiple cores
- FNone of these answers are correct
112Which of the following would be considers an appropriate mitigation for a data hazard? Check all that apply.
- AForwarding a value that is needed before it has been written to it's final location
- BImplementing a delayed branch
- CNot allowing two data access on an instruction
- DImplementation of static branch prediction
- EUse of multiple cores
- FNone of these answers are correct
113The load word instruction requires a stall.
- AVerdadero
- BFalso
114What is the principal of locality?
- AA reference to cache management protocols.
- BIf an item is referenced, items whose addresses are close by will tend to be referenced soon.
- CIf an item is referenced, it will tend to be referenced again soon.
- DPrograms access a relatively small portion of their address space at any instant of time.
- ENone of these answers are fully correct.
115What is temporal locality?
- AA reference to cache management protocols.
- BIf an item is referenced, items whose addresses are close by will tend to be referenced soon.
- CIf an item is referenced, it will tend to be referenced again soon.
- DPrograms access a relatively small portion of their address space at any instant of time.
- ENone of these answers are fully correct.
116What is spatial locality?
- AA reference to cache management protocols.
- BIf an item is referenced, items whose addresses are close by will tend to be referenced soon.
- CIf an item is referenced, it will tend to be referenced again soon.
- DPrograms access a relatively small portion of their address space at any instant of time.
- ENone of these answers are fully correct.
117Which memory hierarchy level, of the ones listed below, is closest to the CPU?
- APrimary storage.
- BSecondary storage.
- CTertiary storage.
- DL2
- EAll of these answers are correct.
118What would happen if the processors main memory was implemented using flash memory.
- ANo effect.
- BThis is not possible.
- CDecreased performance.
- DInsufficient information to answer.
119Given the following program fragment;
for (i=0; i< 1000000; i++)
sum += arr[i];
What kind of locality is exhibited with respect to the variable sum? You may assume all variables have been initialized and set appropriately.- APrincipal of locality.
- BTemporal locality.
- CSpacial locality.
- DNone of these answers are fully correct.
120Given the following program fragment;
for (i=0; i< 1000000; i++)
sum += arr[i];
What kind of locality is exhibited with respect to the variable arr[]? You may assume all variables have been initialized and set appropriately.- APrincipal of locality.
- BTemporal locality.
- CSpatial locality.
- DNone of these answers are fully correct.
121What method is used to track whether the data in cache is valid or not?
- AValid bit.
- BDad bit.
- CCache block.
- DNot tracked.
122A new processor can use either a write-through or write-back cache, selectable through software. Assume the processor will run data-intensive applications with a large number of load and store operations. Which cache write policy should be used?
- AThe software should select the appropriate cache policy dynamically at run-time.
- BWrite-back.
- CWrite-through.
- DInsufficient information to asnwer.
123Select the appropriate choice for each.
SRAM Speed = [blank_start]Fastest, most expensive[blank_end]
SRAM Technology Implementation = [blank_start]Uses logic gates (D flip-flop)[blank_end]
SRAM Typical Use = [blank_start]Cache Memory[blank_end]
DRAM Speed = [blank_start]Fast, expensive[blank_end]
DRAM Technology Implementation = [blank_start]Capacitive Storage[blank_end]
DRAM Typical Use = [blank_start]Computer Main Memory[blank_end]- AFast, expensive
- BCapacitive Storage
- CComputer Main Memory
- DCache Memory
- EUses logic gates (D flip-flop)
- FFastest, most expensive
124With regard to flash memory, check all that apply.
- AVolatile.
- BNon-volatile.
- CAcceptable performance for interactive use.
- DPerformance too slow for interactive use.
125What is the advantage of SDRAM (as compared to DRAM)?
- AAble to create larger memory banks than can be done with SRAM.
- BMake the memory non-volatile (for limited amount of time).
- CElimination of memory read conflicts from multiple accesses.
- DImproved performance.
126Which of the following are true regarding memory banks (i.e. primary memory). Check all that apply.
- ALarger memory banks are faster.
- BLarger memory banks are slower.
- CSmaller memory banks are more power efficient.
- DSmall memory banks are faster.
- ESmaller memory banks are slower.
127What is the purpose or function of the memory hierarchy?
- ASeparate computer storage into a hierarchy based on the number of gates required for implementation.
- BSeparate computer storage into a hierarchy based on memory technologies.
- CSeparate computer storage into a hierarchy based on cost.
- DSeparate computer storage into a hierarchy based on performance / response time.
128The AMD bulldozer processor has the following cache sizes. Which size is most likely to be associated with which cache level.
8192 KB
[blank_start]L3[blank_end]
64 KB
[blank_start]L1[blank_end]
2048 KB
[blank_start]L2[blank_end]- AL3
- BL1
- CL2
129Given a direct-mapped cache that will contain 32,768 bytes of data and four-word blocks (where each word is 4 bytes) and assuming 32-bit addressing.
How many additional bits are required for the overhead associated with the 32,768 bytes of data? Be sure to accommodate for the valid bit. Respond with the total number of bits (no spaces, no commas, no decimal point).
[blank_start]36864[blank_end]
What is the overhead (additional space required) for the 32,768 bytes of data, expressed as a
percentage (i.e., overhead / total required)? Respond with percentage (one decimal point, one digit after decimal point, and include the %)
[blank_start]12.3%[blank_end]- A36864
- B12.3%
130Which of the following is a source of cache misses? Check all that apply.
- ACompulsory.
- BWrite-back.
- CConflict.
- DWrite-through.
- ECapacity.
131Which of the following best describes a compulsory cache miss.
- AMiss penalty.
- BInvalid reference.
- CCold start or process migration, first reference.
- DMultiple memory locations mapped to the same cache location.
- ECache cannot contain all blocks accessed by the program.
132Which of the following best describes a conflict cache miss.
- AMiss penalty.
- BInvalid reference.
- CCold start or process migration, first reference
- DMultiple memory locations mapped to the same cache location.
- ECache cannot contain all blocks accessed by the program.
133Which of the following best describes a capacity cache miss.
- AMiss penalty.
- BInvalid reference.
- CCold start or process migration, first reference.
- DMultiple memory locations mapped to the same cache location.
- ECache cannot contain all blocks accessed by the program.
134When is the dirty bit set to 1?
- AIt is initialized to 1 prior to use.
- BWhen the data value is initially placed in the cache location (to determine validity).
- CWhen the tag value stored in that cache location is changed.
- DWhen the data item stored in that cache location is changed.
135Assuming, a 256 word cache using a 4-byte block, how many bits are in the cache set?
[blank_start]8[blank_end]- A8
136What is paging?
- AOnly implemented on high-end server systems (i.e., super computer centers).
- Bs the software implementation of the hardware device that at run time maps virtual address to physical address.
- CA memory compaction process that eliminates the problems associated with contiguous memory allocation.
- DA memory management scheme that allows processes physical memory to be discontinuous.
137Which of the following is true regarding swapping?
- AThe need for swapping has been eliminated by the availability of cheap RAM storage.
- BAll modern OS's use swapping due to its very high performance.
- CIs part of the hardware device that at run time maps virtual address to physical address.
- DIf there is not enough memory available to keep all running processes in memory at the same time, then some processes who are not currently using the CPU may have their memory swapped out to a secondary storage called the backing store.
138Which of the following is/are true regarding paging? Check all that apply.
- AIs the modern version of the first fit memory allocation strategy.
- BRequires a page size of 4096.
- CEliminates most of the problems of contiguous memory allocation.
- DWorks due to the principal of locality.
139What is the purpose or goal of paging?
- AReduce compulsory misses in main memory.
- BImplement security protocols for main memory to ensure appropriate memory segmentation.
- CIncrease memory performance for executing processes.
- DTo provide for efficient use of main memory for process execution.
140What is the purpose of a Translation Lookaside Buffer (TLB)?
- AReduce compulsory misses in main memory.
- BImplement security protocols for main memory to ensure appropriate memory segmentation.
- CImprove performance by reducing having to go to disk to retrieve a page table entry.
- DTo provide for efficient use of main memory for process execution.
141
It is necessary for all of the pages of a process to be in main memory while the process is executing.- AVerdadero
- BFalso
142The pages of a process in main memory must be contiguous.
- AVerdadero
- BFalso
143Pages must be in a specific order in physical memory.
- AVerdadero
- BFalso
144Pages must be in a specific order in virtual memory.
- AVerdadero
- BFalso
145In the context of paging, which is true regarding a hard fault?
- AIndicates that the page was placed into the free list but not yet swapped out.
- BThe page is not in memory and needs to be read from secondary storage.
- CThe page is already in memory and does not need to be read from secondary storage.
- DNone of these answers are fully correct.
146In the context of paging, which is true regarding a soft fault?
- AThe page is not in memory and needs to be read from secondary storage.
- BThe page is not in memory and can not be found.
- CThe page is already in memory and does not need to be read from secondary storage.
- DNone of these answers are fully correct.
147A certain computer provides its users with a virtual-memory space of 232 bytes. The virtual memory is implemented by paging, and the page size is 4096 bytes. A user process generates the virtual address 1112345610 (0x00a9bb00).
Answer in hex. Note, a hex number must be proceeded with 0x.
What is the tag field?
[blank_start]0xa9b[blank_end]
What is the offset?
[blank_start]0xb00[blank_end]- A0xa9b
- B0xb00
148Given a fixed partitioning scheme with equal-size partitions of 2048 bytes and a total main memory size of 224 bytes. A page table is maintained that includes a pointer to a physical page for each resident process. How many bits are required for the pointer?
[blank_start]13[blank_end]- A13
149Consider a virtual memory system with the following properties:
33-bit virtual address
4 KB pages
31-bit physical address
What is the total size of the page table for each process on this processor, assuming that the valid, dirty, reference, and access bits take a total of 11 bits and that all the virtual pages are in use. Assume that disk addresses are not store in the page table. Respond with megabytes (do not enter MB, one decimal point, exactly two digits after the decimal point).
[blank_start]7.86[blank_end]- A7.86
150What is the total size of the Page Table, in megabytes, based on the following assumptions:
33-bit virtual address
8 KB pages
31-bit physical address
valid and dirty bits -> 1 bit each
reference bits -> 6 bits
access bits -> 2 bits
Respond with megabytes (do not enter MB, one decimal point, exactly two digits after the decimal point).
[blank_start]3.67[blank_end]- A3.67
151What is the size of the TLB in bytes based on the following assumptions:
32-bit virtual address
32-bit physical address
valid and dirty bits -> 1 bit each
reference bits -> 6 bits
access bits -> 2 bits
512 TLB entries
4kb page size
Respond with bytes (do not enter "bytes", just the number, no decimal point, no commas).
[blank_start]3200[blank_end]- A3200
152What are two approaches to parallel processing? Check all that apply.
- AAgile programming.
- BSequential programming.
- CDistributed processing.
- DThreaded programming.
153Which of the following is a key disadvantage when implementing parallel programs? Check all that apply.
- ADecreased performance.
- BIncreased performance.
- CThere are no disadvantages.
- DParallel programs are typically more difficult to write and debug.
154With regard to distributed processing, where do parallel computations occur?
- AOn any available computing device.
- BOn different GPUs.
- COn different cores of the same computer.
- DOn different computers.
155With regard to distributed processing, what is a key limiting factor?
- ASize of the processor caches.
- BProcessor types.
- CNumber of cores available.
- DCommunication speeds.
156With regard to threaded processing, where do parallel computations occur?
- AOn any available computing device.
- BOn different GPUs.
- COn different cores of the same computer.
- DOn different computers.
157With regard to threaded processing, what is a key limiting factor?
- ASize of the processor caches.
- BProcessor types.
- CNumber of cores available.
- DCommunication speeds.
158What is a key advantage of threaded computations?
- AGuarantee of improved performance.
- BAn unlimited number of cores available.
- CInterprocess communication speed.
- DThe possibility of race conditions.
159What is a key risk of threaded computations?
- AGuarantee of improved performance.
- BAn unlimited number of cores available.
- CInterprocess communication speed.
- DThe possibility of race conditions.
160What is the name of the C/C++ library commonly used for threading functions?
- Aiostream
- Biomap
- Cstdio
- Dpthread
161Which of the following best characterizes vector processing?
- AMultiple instruction, single data (MISD).
- BSingle instruction, single data (SISD).
- CSingle instruction, multiple data (SIMD).
- DMultiple instruction, multiple data (MIMD).
162What is an advantage of using the parity approach for RAID 5 and RAID 6 configurations?
- ADoubles the I/O performance but at the cost of havling the usable space.
- BAllows for dynamic (real-time) error detection and correction.
- CNo specific advantage, but is standard practice.
- DLower overall overheard (as compared to mirroring).
163What is RAID? Check all that apply.
- AStripping data by storing data sequentially on blocks on different disks.
- BThe idea of mirroring or shadowing data on multiple different disks.
- CA reference to "just a bunch of disks".
- DRedundant array of inexpensive disks.
- ERedundant array of independent disks.
164What is the key advantage of using RAID 5?
- AAbility to recover from any disk hardware failure.
- BTwofold performance improvement.
- CAbility to recover from a single disk failure.
- DAbility to recover from a multiple (2) disk failure.
165What is the key advantage of RAID 6 over RAID 5?
- AAbility to recover from any disk hardware failure.
- BTwofold performance improvement.
- CAbility to recover from a single disk failure.
- DAbility to recover from a multiple (2) disk failure.
166What is parity?
- AEnsuring an equal number of 1's and 0's to allow for error detection.
- BFor a number the fact of being even or odd (reference, Google).
- CRefers to a technique for detection and error correction (and is used for RAID 2 configurations).
- DRefers to a technique for checking whether data has been lost or corrupted when it's stored, transmitted, or moved.
167Does the order the data bytes are XOR'ed matter for the final result?
- AYes.
- BNo.
- CDepends on the specific application.
168Given the following data values;
D1 = 10100101
D2 = 11110000
D3 = 00111100
D4 = 10111001
What would be the parity byte? Must precede the answer with the 0b (for binary).
[blank_start]0b11010000[blank_end]- A0b11010000
169Given the following data values;
D1 = 0xD2
D3 = 0xA5
D4 = 0x65
And a parity byte value of PB = 0xA6
What would be the missing byte for D2? Must precede the answer with the 0x (for hex).
[blank_start]0xB4[blank_end]- A0xB4
170What is an appropriate application of Amdahl's Law?
- AProvides a technical base-line for measuring the performance of parallel programs and comparing them to non-parallel programs.
- BEstablishes the maximum number of parallel components for a given problem.
- CNotes that computers double in performance every 18-24 months.
- DIdentifies potential performance gains from adding additional computing cores.
171Given a 6-processors multiprocessor system and an application that has 60% of the code parallelized, what is the approximate effective speed-up?
speedUp(P,N)=1 / (1−P)+ (P/N)
[blank_start]2[blank_end]- A2
Información
- Descripción
- Test sobre grasgr4awgs, creado por geahu gehaoigeaio el 12/05/2021.
- Autor
- geahu gehaoigeaio
- Idioma
- English
- Visitas
- 3
- Valoración
- Aún sin valoraciones Valora este test