Flashcards
ECE 483 Exam 1
Cards in this deck (47)
- 1Why do CMOS processes have a range of metal layers/metal stack?CMOS processes offer a range of metal layers that can be used for interconnection of individual devices such as transistors, resistors and capacitors.
- 2What separates metal layers in CMOS processes?Each of the metal layers are separated by a dielectric
- 3How are different metal layers connected to each other in CMOS?Different metal layers are connected to each other using vias (i.e. via shorts M1 to M2).
- 4What's an example of a routing strategy?Use M1 within cells
Use M2 for vertical routing
Use M3 for horizontal routing - 5What are examples of resistive layers used in CMOS?Resistive layers include diffusion (n+ or p+), polysilicon, n-well and metals.
- 6Resistance equation. What parameters are fixed by the process technology and which are chosen by the designer?R = (rho/t) * (L/W). rho and t are fixed by the technology. W and L are chosen by the designer.
- 7Sheet resistance definition and resistance equation in terms of sheet resistance.R = R_sheet * (L/W)
- 8Total resistance equation including contact resistance.
- 9How does the dogbone layout help?The dogbone layout reduces contact resistance such that:
Rcontact << R_sheet * (L/W) - 10To implement large resistors, what layout is used and why?Serpentine layout is used for large resistors because it increases L.
- 11Sensitivity analysis steps.1. Solve equation in terms of the desired variable.
2. Using R = R_sheet * L/W as an example, set ΔR = (∂R/∂R_sheet) * ΔR_sheet + (∂R/∂L) * ΔL + (∂R/∂W) * ΔW.
3. Solve derivatives using the equation in #1.
4. Plug derivative solutions back into equation #2 and solve for Δvariable/variable - 12Resistance as a function of temperature.
- 13Resistance as a function of voltage.
- 14Units for TC and VCTC: ppm/degrees C
VC: ppm/V - 15Capacitance of parallel plate capacitor in CMOS.
- 16Capacitance per unit area and units.
- 17Relative capacitance error due to rough edges in area.where Δe = Δx = Δy
- 18Capacitance as a function of voltage and temperature.
- 19Accumulation mode in NMOS.VG < 0. Positive charges accumulate near the top of the substrate at the gate due to the negative gate voltage. This behaves like a capacitor.
- 20Depletion mode in NMOS.VG > 0. Fixed negative charges/ions are near the gate since mobile positive charges are pushed away into the p-substrate. Device is depleted of any free charge carriers since all of them are pushed away.
- 21Inversion mode in NMOS.VG >> 0. Conductive layer forms with free electrons at the surface of the substrate and current can flow when a voltage is provided.
- 22What is the threshold voltage VTH?VTH is the gate voltage needed to make the concentration of electrons in the channel equal to the concentration of holes in the p-substrate.
- 23MOS triode region equation
- 24MOS saturation region equation
- 25Saturation equation with channel length modulation.where λ * V_DS = ΔL/L
- 26Overdrive voltage equation for PMOS.
- 27MOS incremental model
- 28Common Source Amplifier
- 29GM and R_OUT for common source amp
- 30gm equationgm = 2 * I_D / V_OV
- 31Resistance looking into source of MOSFET without drain resistance.
- 32Resistance looking into source of MOSFET with drain resistance.
- 33Resistance looking into drain
- 34Resistance looking into drain with source resistance
- 35Common Source Amp with source degeneration GM.GM = 1 / R_S
- 36Common Gate Amp
- 37GM of Common Gate AmpGM = - gm
- 38GM of Common Gate Amp with source resistance
- 39Cascode Stage
- 40GM of Cascode StageGM = gm1
- 41Folded Cascode Stage
- 42GM of folded cascode stageGM = gm1
- 43Differential mode gain equation. What is ideal A_DM?
- 44Common mode gain equation. What is ideal A_CM?
- 45Common mode to differential mode gain equation. What is ideal A_CDM?
- 46Differential to common mode gain equation. What is ideal A_DCM?
- 47CMRR Equation. What is ideal CMRR?
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- Flashcards on ECE 483 Exam 1, created by bam bam on 26/02/2022.
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