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Ingeniería Económica

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Truth Table, inputs-outputs

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Mind Map by cristinaaa.perez, updated more than 1 year ago

	Created by cristinaaa.perez over 9 years ago

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Resource summary

Truth Table, inputs-outputs

MINILOG
1. SOP
2. POS
  1. Simplify the equations
    1. Transform into a VHDL file
      1. Example: P <= (X and Y and Z)
      2. ispLEVER
        Implementate
        ActiveHDL
        Simulations and results

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