Mind map
Truth Table, inputs-outputs
Map content
Truth Table, inputs-outputs
MINILOG
- SOP
- POS
- Simplify the equations
- Transform into a VHDL file
- Example: P <= (X and Y and Z)
- ispLEVER
- Implementate
- ActiveHDL
- Simulations and results
- ActiveHDL
- Implementate
- Transform into a VHDL file
- Simplify the equations
- SOP