ICT2104 Chapter 4: Interrupts

Meixi Lim
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Meixi Lim
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ICT2104 Chapter 4: Interrupts
  1. CPU Processing Stages
    1. RESET State: CPU and internal peripheral modules are initialised and stopped
      1. Exception-Processing State: Transient state that occurs when CPU alters normal processing flow due to exception source
        1. Program Execution State; CPU executes program instructions in sequence
          1. Bus-Released State: Occurs when bus has been released in response to bus request from a bus master; CPU halts operations
            1. Program Stop State: Power-down state which CPU stops operating
            2. Reset and Interrupts
              1. Program Execution
                1. PC: Points to next instruction to be executed
                  1. SR: Subsequent instruction make use of altered values of SR to carry out branch condition
                    1. SP: Storing of information that cannot be over-written within ISR
                    2. RESET: Allows fetching the first instruction to be executed after a power-up
                      1. Other Reset Triggers
                        1. Only triggers when button is released
                        2. Power-On Reset
                          1. Is a NMI
                            1. Reset Signal must be active for at least 2us
                        3. IVT and Priority
                          1. Reset Address
                            1. Fixed Vector
                              1. Auto-Vectored
                            2. MSP430 port interrupt registers
                              1. Types
                                1. NMI: Cannot be disabled by GIE; Used for high priority events
                                  1. MI: GIE must be set, can be switched off by software
                                  2. Interruptible Ports: Port 1 & Port 2
                                    1. PxIFG: Interrupt Flag
                                      1. Bit 1: Interrupt pending
                                        1. Bit 0: No interrupt pending
                                        2. PxIE: Interrupt Enable
                                          1. Bit 1: Interrupt enabled
                                            1. Bit 0: Interrupt disabled
                                            2. PxIES: Interrupt Edge Select
                                              1. Bit 1: Falling Edge
                                                1. Bit 0: Rising Edge
                                              2. #pragma vector = PORTx_VECTOR
                                                1. During interrupt event
                                                  1. PC points to next instruction and is pushed with SR to stack
                                                    1. SR is cleared (except SCG0) and GIE flag
                                                      1. RETI returns to original program flow, pops SR and PC
                                                      2. ISR processing time should be < interrupt's request time interval
                                                        1. To avoid stack overflow, collapsing program
                                                        2. Interrupt Latency: Time between event beginning and ISR execution
                                                        3. Interrupt identification and priority determination
                                                          1. Identification Methods
                                                            1. Non-vectored
                                                              1. Unable to identify which device directly
                                                                1. CPU has to check which device within ISR
                                                                2. Vectored-Based
                                                                  1. Auto-Vectored
                                                                    1. Vector number is predefined by assigning an interrupt to a vector number
                                                                      1. Generated internally by CPU
                                                                        1. Only one IRQ line, no acknowledgement
                                                                          1. Only 1 interrupt / IRQ line
                                                                          2. Full-Vectored
                                                                            1. Can be supplied by device itself
                                                                              1. Provided by device
                                                                                1. IRQ + IACK lines: Handshake logic
                                                                                  1. Flexible as device can send different #
                                                                                    1. Can have > 1 IRQ line
                                                                                    2. Each interrupt is uniquely identified with a different vector number
                                                                                      1. More flexible in providing priority and masking of bits
                                                                                        1. Requires a lot of hardware resources to resolve additional issues (i.e. masking)
                                                                                      2. Priority Handling
                                                                                        1. Daisy Chain
                                                                                          1. The closer it is to CPU, the higher the priority
                                                                                            1. Hardwired, difficult to balance services among devices
                                                                                            2. Interrupt Controller
                                                                                              1. Programmable support peripheral, allows handling of requests from multiple devices
                                                                                                1. Flexible in terms of priority management
                                                                                            3. Interrupt processing stages and latency
                                                                                              1. Stages
                                                                                                1. 1. Complete any currently executing instructions
                                                                                                  1. 2. Push PC to stack
                                                                                                    1. 3. Push SR to stack
                                                                                                      1. 4. Select highest priority interrupt if multiple interrupts occured
                                                                                                        1. 5. IFG resets automatically on single-source flag. Otherwise, IFG remain set.
                                                                                                          1. 6. Clear all bits of SR (except SCG0) and GIE.
                                                                                                            1. 7. Load content of interrupt vector into PC; continues ISR.
                                                                                                            2. Latency
                                                                                                              1. At least 6 clock cycles before ISR executes (see stages)
                                                                                                                1. RETI requires 5 cycles
                                                                                                                  1. 1. Pop SR and GIE from stack
                                                                                                                    1. 2. Pop PC from stack and continues execution from where it was interrupted
                                                                                                                2. Interrupt driven I/O
                                                                                                                  1. Maximum interrupt handler execution time permitted: Time between each interrupt
                                                                                                                  2. Multiple interrupts and interrupt nesting
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