Digital Systems

Digital Systems

1. Foundations

   • real world
     • analogue
     • measurable
     • theoretically infinite precision
   • digital world
     • discrete sets of values
   • binary digital systems
     • only 2 possible values
       • 0/1
       • True/False
       • High/Low

2. Fundamental mathematics principles

   • operators
     • AND OR NOT
   • Laws
     • Associativity –Commutativity –Distributivity –Identity & Annihilation –Complementation
   • Logic Gates
     • • Gates combined to form larger circuits
         • equations
         • Truth tables

3. Types

   • Combinational Logic
     • – Implements a block of logic. E.g. a function
       • – The output depends entirely on the current value of the inputs
         • – Can capture the functionality using maths, truth tables, K ‐maps • Can be: Logical, e.g. and, or; arithmetic, e.g. add, absolute
   • Sequential Logic
     • – Feedback (or storage) is introduced so output also depends on previous values
       • – Can capture more complex behaviour •Latches, flip ‐flops, counters, shift registers
         • – Synchronous logic is clock edge-driven – Synchronous logic is easier to analyse than asynchronous

4. Building Computation –Two classes of operation

   • Combinational
     • –Arithmetic –Comparision
   • Sequential
     • • Take values in turn •Increment a counter •Store a result
   • Computation is accomplished using an algorithm, --> a step by step procedure for calculation
     • – Transformations/Functions: combinational functions that operate on input data and produce an output
     • – Storage: a unit that stores a value or some state

5. Understanding the Design Flow

   • – The process of turning an HDL description into working hardware consists of a number of steps
     • The input is correctly written synthesisable code
     • The desired output is a bitstream that configures the FPGA to implement the circuit
   • • Architecture Design
       • Requirements
         • What technology to use
         • What function(s) is required?
         • time should be taken to compute the function?
         • How large should the implemented circuit be?
         • How much power should be consumed?
         • How accurate do the results need to be?
     • • • • • Check that the timing constraints have been met
             • Analyse critical paths if there is a need to improve timing
             • Simulate the final placed and routed design using the original testbench if desired
           • Takes the mapped netlist generated by the Mapper
           • Assigns each instance of a basic block to a location on the FPGA
           • Configures the routing to connect those blocks as per the netlist
           • Iterates this process multiple times to find a placement and set of routes that meet the timing requirements
         • decides how to implement the components on the target architecture:
           • Combinational logic is converted into look ‐up tables (LUTs)
           • Synchronous components are mapped to the registers inside CLBs
           • Arithmetic operators are mapped to logic
           • Memories are mapped to either Block RAMs or distributed logic
           • Logic that can be implemented using hard blocks in the FPGA is mapped to them
       • • Check that the circuit fits the target device
         • Obtain an initial estimate of the timing performance
         • Ensure all the code we entered is synthesisable
         • Ensure no logic has been trimmed off unintentionally
       • where the tools process the HDL description
         • The behavioural description is translated into hardware blocks
         • Combinational logic is simplified and minimised
         • Basic structures such as multiplexers and memories are inferred
           • result is a netlist: a low ‐level representation of the circuit using basic building blocks
         • Arithmetic operations are expanded into simple representations
     • • Test individual components, moving up the hierarchy
       • Check that the design implements the required behaviour

Imagens e arquivos do mapa