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Quiz

CPSC 313 Unit 3 Memory MIDTERM COVERAGE

Zim Brightwood 9 perguntas Atualizado em 5 jan 2017

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Perguntas do quiz (9)

  1. 1Build the Memory Hierarchy!
    L0: [blank_start]Registers[blank_end]
    L1: [blank_start]L1 cache[blank_end] ([blank_start]SRAM[blank_end])
    L2: [blank_start]L2 cache[blank_end] (SRAM)
    L3: [blank_start]Main memory[blank_end] ([blank_start]DRAM[blank_end])
    L4: [blank_start]Local secondary storage[blank_end] ([blank_start]local disks[blank_end])
    L5: [blank_start]Remote secondary storage[blank_end] (tapes, web servers, distributed file systems)

    L0 to L2 is [blank_start]smaller, faster, costlier[blank_end] per byte
    L3 to L5 is [blank_start]larger, slower, cheaper[blank_end] per byte
    1. ARegisters
    2. BL0 cache
    3. CL1 cache
    4. DL2 cache
    5. EMain memory
    6. FLocal secondary storage
    7. GRemote secondary storage
    8. HSRAM
    9. IDRAM
    10. Jlocal disks
    11. Ksmaller, faster, costlier
    12. Llarger, slower, cheaper
    13. MRRAM
    14. NL3 cache
    15. OL4 cache
    16. PL5 cache
  2. 2Static RAM is smaller, faster, and costlier per byte
    1. AVerdadeiro
    2. BFalso
  3. 3DRAM is smaller, faster, cheaper per byte
    1. AVerdadeiro
    2. BFalso
  4. 4Reference locality exists when data or code accesses tend to be near each other [blank_start]temporally[blank_end] or [blank_start]spatially[blank_end]
    1. Atemporally
    2. Bspatially
    3. Creferentially
    4. Dlocally
    5. Esparingly
    6. Fsparsely
    7. Gmoderately
    8. Hdensely
  5. 5[blank_start]Temporal[blank_end] locality exists when there are multiple accesses to the same memory within a short interval
    1. ATemporal
    2. BReferential
    3. CTrump
    4. DClinton
    5. ESpatial
  6. 6Caches are small storage devises that store subsets of larger storage devices
    1. AVerdadeiro
    2. BFalso
  7. 7Prefetching fetches data into the cache after it is accessed
    1. AVerdadeiro
    2. BFalso
  8. 8A cache hit is an access that [blank_start]can[blank_end] be satisfied by a cache while is miss is an access that [blank_start]cannot[blank_end] be satisfied by a cache
    1. Acan
    2. Bcannot
  9. 9How do we handle cache misses?
    1. APropogate down hierarchy, stop at hit in lower level, propagate back up and add data to each cache on the way
    2. BPropogate down hierarchy, stop at hit in lower level, propagate back up
    3. CPropogate up hierarchy, stop at hit in higher level, propagate back down and add data to each cache on the way
    4. DPropogate up hierarchy, stop at hit in higher level, propagate back down

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Descrição
Computer Science Quiz sobre CPSC 313 Unit 3 Memory MIDTERM COVERAGE, criado por Zim Brightwood em 22-10-2016.
Idioma
English
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17
Histórico
Criado em 22 out 2016 · atualizado em 5 jan 2017
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