Quiz
CSA GOS 1
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Questions in this quiz (200)
1A bipolar transistor has terminals labeled
- Agate
- Bsource and drain
- Cbase, collector
- Demitter
2Choose advanced cache optimizations
- AGiving Reads Priority over Writes
- BLarger Cache Size
- CHardware Prefetching of Instructions and Data
- DMerging Write Buffer
- ECritical Word First and Early Restart
3Choose basic cache optimizations
- ACompiler-Controlled Prefetching
- BNonblocking Caches
- CSmall and Simple First-Level Caches
- DMultilevel Caches
- EAvoiding Address Translation during Cache Indexing
4Choose data dependences
- ARead-After-Read
- BRead-After-Write
- CWrite-After-Write
- DWrite-After-Read
5Choose the access method(s)
- AParallel Access
- BIndirect Access
- CRandom Access
- DDirect Access
- ESequential Access
- FSecondary Memory
6Choose the characteristics of CISC processors
- Alarge number of instructions
- Bsupport many addressing modes
- Cmore elaborate way of accessing data
- Dless number of instructions
- Einstructions are of fixed length
- Ffew addressing modes
7Choose the characteristics of Harvard architecture
- Aseparate program and data memories
- Bseparated buses allow one instruction to execute while the next instruction is fetched
- Cdata and instructions mustn't have the same width
- Done memory for data and program
- ECPU provides address to get data or instruction
- Fdata and instructions must have the same width
8 Choose the characteristics of RISC processors
- Aless number of instructions
- Binstructions are of fixed length
- Cfew addressing modes
- Dlarge number of instructions
- Esupport many addressing modes
- Fmore elaborate way of accessing data
9Choose the characteristics of Von Neumann architecture
- Aone memory for data and program
- BCPU provides address to get data or instructions
- Cdata and instructions must have the same width
- Dseparate busses, can be accessed simultaneously
- Eseparated buses allow one instruction to execute while the next instruction is fetched
- Fdata and instructions mustn't have the same width
10Choose the components of SSD
- AController
- BAddressing
- CData buffer/cache
- DData size
- EMemory hierarchy
11Choose the element(s) of cache design
- ATag
- BLatency
- CAMAT
- DMapping Function
- EReplacement Algorithm
- FNumber of Caches
12Choose the element(s) of cache design
- ATag
- BAMAT
- CLatency
- DCache Size
- ELine Size
- FNumber of Caches
13Choose the feature(s) of first generation com uter architecture
- AMagnetic core memory
- BSemiconductor memory
- CMachine code
- DVacuum tubes
- EAssembly language
14Choose the feature(s) of fourth generation
omputer architecture- AUse of drum memory or magnetic core memory
- BUse of cache memory
- CSmallest in size
- DObject-Oriented programming
- EWide spread use of data communication
15Choose the feature(s) of second generation computer architecture
- AHigh level languages
- BTransistors
- C2 Kb memory, 10 KIPS
- D2 Mb memory, 5 MIPS
- EDifferent types of supported instructions
16Choose the feature(s) of third generation computer architecture
- AObject-Oriented programming
- BFloating point arithmetic
- CGraphics
- DTimesharing
- EUse of cache memory
17Choose the key characteristics of computer memory systems
- ALocation
- BUnit of Transfer
- CAccess Method
- DStalling
- EHazards
18Choose the key characteristics of computer memory systems
- ACapacity
- BPerformance
- COrganization
- DInstruction Fetch
- EInstruction Decode
19Choose the legal name(s) in assembly
- A@variable_name
- Bvariable?
- Cvariable&name
- Dvariable name
- E1variable
20Choose the performance factor(s)
- ACache Size
- BLine Size
- CInstruction Count
- DNumber of Processor Cycles
- EMapping function
- FLatency
21Choose the performance factor(s)
- ACache Size
- BLine Size
- CInstruction Count
- DNumber of Processor Cycles
- ENumber of memory references
22Choose the physical characteristic(s) of disk systems
- ADisk system implementstion
- BDisk Size
- CHead Mechanism
- DHead Motion
- EDisk Portability
23Choose the right formula for AMAT
- AAMAT \= Hit time + Miss rate + Miss penalty
- BAMAT \= Hit time * Miss rate + Miss penalty
- CAMAT \= Hit time * Miss rate * Miss penalty
- DAMAT \= Hit time + Miss rate * Miss penalty
24Choose the system attribute by which the performance factors are influenced
- ACache size
- BUnit of Transfer
- CCompiler Technology
- DProcessor Implementation
- ECache and memory hierarchy
25Choose the type (s) of Transistors
- AAn amplifier transistor
- BA base-collector transistors
- CA bipolar transistor
- DA field-effect transistor
26Choose the type(s) of auxiliary memory
- AFlash Memory
- BOptical Disk
- CHard Drive
- DSSD
- ERAM
27Choose two types of models for a computing machin
- AHarvard architecture
- BVon Neumann architecture
- COxford architecture
- DStanford architecture
28Program executes 0.375 sec nds on a CPU with 2 360 000 instructions and 5 cycles per instruction. Find the clock rate of this CPU
- A0,314 GHz
- B0,3501 GHz
- C0,4501 GHz
- D0,467 GHz
- E0,3503 GHz
29Convert binary 01101101 to decimal
- A109
- B87
- C91
- D134
- E113
30Convert binary 1100111 to decimal
- A103
- B100
- C95
- D130
- E110
31How many elements of cache design are there?
- A2
- B4
- C5
- D6
- E7
32How many generations of computer architecture re there?
- A4
- B3
- C2
- D1
- E5
33Convert decimal 230 to the binary
- A011000110
- B011100110
- C101100110
- D011100111
34How many number systems are exist?
- A4
- B3
- C2
- D1
- E5
35How many number systems are there?
- A1
- B2
- C3
- D4
36Convert decimal 74 to the binary
- A011011110
- B01001010
- C101101110
- D011101110
37How many physical characteristics of disk sys ems are there?
- A4
- B5
- C2
- D3
- E6
38How the central terminatio
point for data channels, the CPU, and memory is called. It schedules access to the memory from the CPU and data c annels, allowing these devices to act independently- ATransistor
- BMultiplexor
- CIntegrated circuit
- DResistors
- ECapacitors
39Convert decimal value 877 to hexadecimal
- A36D
- B38A
- C36B
- D38C
- E36A
40Convert hexadecimal value 1E7 to decimal
- A478
- B487
- C423
- D243
- E278
41Match the statements with the right architecture Harvard
- ASeparate program and data memories and separate busses, can be accessed simultaneously
- BSeparated buses allow one instruction to execute while the next instruction is fetched
- CData and instructions mustn't have the same width
- DData and instructions must have the same width
- ECPU provides address to get data or instructions
- FOne memory for data and program, with one bus for both
42How the stage in which the results o
the operation are written to the destination register is called?- AInstruction Fetch
- BWrite Back
- CInstruction Decode
- DExecution
- EMemory read/write
43Convert hexadecimal value 1F9 to decimal
- A525
- B505
- C510
- D243
- E278
44Match the statements with the right architecture Von Neumann
- AOne memory for data and program, with one bus for both
- BCPU provides address to get data or instructions
- CData and instructions must have the same width
- DSeparate program and data memories and separate busses, can be accessed simultaneously
- ESeparated buses allow one instruction to execute while the next instruction is fetched
- FData and instructions mustn't have the same width
45An instruction may have one or more operands
- ATrue
- BFalse
46How we call the thing that is connects major computer components (processor, memory, I/O)?
- ASystem connector
- BSystem controllers
- CSystem bus
- DSystem interconnector
47In which cache memory mapping technique any block from main memory can be placed anywhere in the cache?
- AAssociative Mapping
- BSet Associative Mapping
- CDirect Mapping
48Convert hexadecimal value AC to decimal
- A175
- B172
- C171
- D170
- E179
49Match the three performance parameters with their definitions Access time (latency)
- AThis is the time it takes to perform a read or write operation, that is, the time from the inst nt that an address is presented to the memory to the instant that data have been stored or made available for use
- BThis concept is primarily applied to random-access memory and consists of the access time plus any additional time required before a second access can commence.
- CThis is the measurement at which data can be transferred into or out of a memory unit
50Digital circuits are inflexible and slower, because they are technology dependent
- ATrue
- BFalse
51In which cache mem ry mapping technique any memory block is mapped to exactly one block in the cache?
- ADirect Mapping
- BSet Associative Mapping
- CAssociative Mapping
52Match the three performance parameters with their definitions Memory cycle time
- AThis is the time it takes to perform a read or write operation, that is, the time from the inst nt that an address is presented to the memory to the instant that data have been stored or made available for use
- BThis concept is primarily applied to random-access memory and consists of the access time plus any additional time required before a second access can commence.
- CThis is the measurement at which data can be transferred into or out of a memory unit
53Four bits make octal digit::[html]Four bits make octal digit
- ATrue
- BFalse
54Convert hexadecimal value DAD to decimal
- A3500
- B3501
- C4501
- D4500
- E3503
55In which cache mem ry mapping technique any memory block mapped to subset of cache locations?
- ASet Associative Mapping
- BDirect Mapping
- CAssociative Mapping
56Match the three performance parameters with their definition Transfer rate
- AThis is the measurement at which data can be transferred into or out of a memory unit
- BThis concept is primarily applied to random-access memory and consists of the access time plus any additional time required before a second access can commence.
- CThis is the time it takes to perform a read or write operation, that is, the time from the inst nt that an address is presented to the memory to the instant that data have been stored or made available for use
57Into how many parts a pro ram (or algorithm) which can be parallelized can be split up?
- A3
- B4
- C5
- D2
58IBM System/360 Model 91 was introduced in 1966
- ATrue
- BFalse
59Convert the binary value 111011 to decimal
- A59
- B58
- C56
- D60
- E69
60In 1976 Apple II computer model was released
- ATrue
- BFalse
61There are three types of hazar s that can happen while pipelined execution. Match the hazards with their definitions\ Structural hazards
- Adifferent instructions in different stages (or the same stage) conflicting for the same resource
- Ban instruction cannot continue because it needs a value that has not yet been generated by an earli r instruction
- Cfetch cannot continue because it does not know the outcome of an earlier branch - special case f a data hazard
62Convert this number systems DEC(4591) to HEX?
- A11EF
- B12832
- C43B1
- D7DE1
63In assembly language you can express data only in binary and decimal
- ATrue
- BFalse
64Memory is organized into un ts of data, called records; access must be made in a specific linear sequence
- ASequential access
- BWord
- CAddressable units
- DUnit of transfer
- EDirect access
65There are three types of hazar s that can happen while pipelined execution. Match the hazards with their definitions Data hazards
- Adifferent instructions in different stages (or the same stage) conflicting for the same resource
- Ban instruction cannot continue because it needs a value that has not yet been generated by an earli r instruction
- Cfetch cannot continue because it does not know the outcome of an earlier branch - special case f a data hazard
66In assembly language, you can skip the name of variable
- ATrue
- BFalse
67Convert this number systems DEC(8425) to HEX?
- A20E9
- B7DE1
- CA31F
- D2811
68In assembly statement name and comment are mandatory
- ATrue
- BFalse
69There are three types of hazar s that can happen while pipelined execution. Match the hazards with their definitions Control hazards
- Adifferent instructions in different stages (or the same stage) conflicting for the same resource
- Ban instruction cannot continue because it needs a value that has not yet been generated by an earli r instruction
- Cfetch cannot continue because it does not know the outcome of an earlier branch - special case f a data hazard
70MIC stands fo
- Amini integrated core
- Bmany integrated core
- Cmain integrated core
- Dmany interaction core
- Emain interaction core
71Convert this number systems HEX (11EF) to DEC
- A4591
- B1012
- C1312
- D1514
72In execution stage identification of the operation is performed
- ATrue
- BFalse
73_____________ is a speci l purpose system that is used to perform one or few dedicated functions.
- ADistributed systems
- BEmbedded systems
- CUltra-Large-Scale Systems
- DCentralized systems
- EUbiquitous systems
74PCI stands for
- APower Control Interface
- BPeripheral component interconnect
- CProperty Casualty Insurers
- DProgrammable Communications Interface
75Convert this number systems HEX (5123) to DEC?
- A20771
- B13456
- C14512
- D10602
76In two-operand instruction, the first operand is source and the second operand is destination
- ATrue
- BFalse
77Processor can simultaneously work
on multiple instructions. How this technique called?- APipelining
- BBranch prediction
- CData flow analysis
- DSpeculative execution
- ENone of the above
78_____________ is the am unt of time it takes the program to perform in seconds
- AElapsed time
- BOverall time
- CEstimate time
- DExecution time
- EProcess time
79In virtual memory, memory can be
used efficiently because a section of program always loaded- ATrue
- BFalse
80A common measure of performan e for a processor is the rate at which instructions are executed, called
- ACPI
- BClock Rate
- CMFLOPS
- DMIPS
81Specifies the address in mem ry of the word to be written from or read into the MBR
- AMemory address register (MAR)
- BMemory buffer register (MBR)
- CInstruction register (IR)
- DInstruction buffer register (IBR)
- EProgram counter (PC)
82For random-access memory, the time it takes to perform a read or write operation is called
- AClock Rate
- BCPI
- CAccess Time
- DLatency
83Measures such as MIPS and MFLOPS have proven adequate to evaluating the performance of processors.
- ATrue
- BFalse
84SSD stands for
- ASolid State Drive
- BSolid State Driver
- CSpeed State Drive
- DSpeed State Driver
85A processor is driven by a clock with a co stant frequency f or, equivalently, a constant cycle time t, where t \= 1/f\
- AInstruction execution rate
- BInstruction execution cycle
- CInstruction execution time
- DInstruction execution period
- ENone of the above
86Name field of assembly statement is not case sensitive
- ATrue
- BFalse
87How a memory unit accessed by contents is called?
- AAssociative Memory
- BContent Addressable Memory
- CAuxiliary Memory
- DCache Memory
- EVirtual Memory
88Octal and hexadecimal numbers are hard on use and conversion
- ATrue
- BFalse
89A single, self-contained transistor is called ________.::[html]A single, self-contained transistor is called ________.
- Aintegrated circuit
- Bmicrochip
- Cdiscrete component
- Dsingle transistor
- Esmall-scale integration
90Stage in which the instruction is etched from memory and placed in the instruction register called
- AMemory read/write
- BInstruction Decode
- CExecution
- DWrite Back
- EInstruction Fetch
91Physical address used by program, and which OS must translate into virtual address
- ATrue
- BFalse
92The "natural" unit of organization of memory
- AWord
- BSequential access
- CAddressable units
- DUnit of transfer
- EDirect access
93Pipelining can only be implemented on hardware
- ATrue
- BFalse
94A state in which data reques ed for processing by a component or application is found in the cache memory
- ACache hit
- BCache miss
- CCache set
- DCache overwrites
- ECache access time
95ROM is the place in a computer here the operating system, application programs, and data in current use are kept
- ATrue
- BFalse
96 Choose the physical characteristic(s) of disk systems?
- ADisk system implementstion
- BDisk Size
- CHead Mechanism
- DPlatters
- ESides
97The basic element of a semiconductor memory is
- AMemory cell
- BCache memory
- CRAM
- DDRAM
- ENone of the above
98SSD is over 10 times faster than the spinning disks in HDD
- ATrue
- BFalse
99AMAT stands for
- AAverage memory access time
- BAutomatic Message Accounting Transmitter
- CAsymptotic Mean Acquisition Time
- DAbsolute memory access time
100Most transistors are made from
- Agilt
- Bmetal
- Cvery pure silicon
- Dgermanium
101The first bipolar junction transistors were invented by
- AHerbert Mataré and Heinrich Welker
- BBell Labs' William Shockley
- CMorris Tanenbaum
- DMohamed Atalla
102SSDs are more susceptible to physical shock and vibration
- ATrue
- BFalse
103Amdahl's law\
- ASpeed up\= 1/(1 + f ) * f/N
- BSpeed up\= 1/(1 - f ) * f/N
- CSpeed up\= 1/(1 - f ) - f/N
- DSpeed up\= 1/(1 - f ) + f/N
- ESpeed up\= 1/(1 + f ) + f/N
104SSDs are susceptible to mechanical wear
- ATrue
- BFalse
105The first working device to be built was a point-contact transistor invented in
- A1956
- B1959
- C1947
- D1926
106Process of instruction execution is divided into two or more steps, called
- Apipelining
- Bpipe stages
- Cpipe segments
- Dinstruction execution
- Epipeline hazard
- FWrite Back
107Static RAM has a reduced power consumption, and a large storage capacity
- ATrue
- BFalse
108An instruction pipeline increases the erformance of a processor by overlapping the processing of several different instructions. How many stages it is con ist of
- A6
- B3
- C5
- D7
- E4
109The processor responds by suspe ding operation of the current program, branching off to a program to service that particular I/O device, known as __ ______________, and resuming the original execution after the device is serviced. Which of the following will be th
missing word\:- Ainterrupt handler
- Binterrupt cycle
- Cdisabled interrupt
- Dinterrupt request
110The "natural" unit of organization of memory is called block
- ATrue
- BFalse
111Choose hazard for the followi g definition\: an instruction cannot continue because it needs a value that has not yet been generated by an earlier ins ruction{
- AData
- BStructural
- CControl
112The advantage of virtual memory is that it takes less time to switch between applications because of additional memory
- ATrue
- BFalse
113Choose hazard for the following defi ition\: different instructions in different stages (or the same stage) conflicting for the same resource
- AStructural
- BData
- CControl
114Select cache optimizations to increase the Cach Bandwidth
- ANonblocking Caches
- BMultibanked Caches
- CPipelined Cache Access
- DMultilevel Caches
- ESmall and Simple First-Level Caches
115The rate at which data can be transferred into or out of a memory unit is called
- ATransfer time
- BTransfer Rate
- CMIPS
- DFLOPS
- EMFLOPS
116The assembler translates names into memory addresses
- ATrue
- BFalse
117The execution time of a program clearly depends on the number of instructions
- ATrue
- BFalse
118Choose hazard for the follo ing definition\: fetch cannot continue because it does not know the outcome of an earlier branch - special case of a d ta hazard
- AControl
- BStructural
- CData
119The time between pulses called?
- ACycle time
- BClock speed
- CClock rate
- DClock cycle
120Choose the component of SD for the following definition\: High speed RAM memory components used for speed matching and to increased d ta throughput
- AData buffer/cache
- BFlash Memory Components
- CAddressing
- DController
- EError Correction
121The L2 cache is faster and typically larger than the L1 cache, and the L3 cache is slower and typically larger than the L2 cache
- ATrue
- BFalse
122Select cache optimizations to reduce hit time (both basic and advanced)
- AAvoiding Address Translation during Cache Indexing
- BSmall and Simple First-Level Caches
- CWay Prediction
- DCompiler Optimizations
- ECompiler-Controlled Prefetching
123The use of the _______ defines the third eneration of computers.
- ASmall and medium-scale integration
- BTransistor
- CVacuum tube
- DLarge-scale integration
- EVery-large-scale integration
124Choose the component of SS
for the following definition\: Logic for error detection and correction- AError Correction
- BAddressing
- CData buffer/cache
- DController
- EFlash memory components
125The L2 cache is slower and typically larger than the L1 cache, and the L3 cache is slower and typically larger than the L2 cache
- ATrue
- BFalse
126The world's first general-purpos
microprocessor. It was used in the first personal computer, the Altair.- A8070
- B8080
- C8086
- D8090
127Select cache optimizations to reduce miss penalty
- AMultilevel Caches
- BGiving Reads Priority over Writes
- CWay Prediction
- DHigher associativity
128This technique enables the p ocessor to keep its execution engines as busy as possible by executing instructions that are likely to be needed
- ABranch prediction
- BData flow analysis
- CPipelining
- DSpeculative execution
129The more clock rate of processor, the faster is processor
- ATrue
- BFalse
130Choose the component o SSD for the following definition\: Logic that performs the selection function across the flash memory components
- AAddressing
- BFlash Memory Components
- CController
- DError Correction
131The particular block is currently being stored is called tag
- ATrue
- BFalse
132Typically all operations performed by a p ocessor begin with the
- Apulse of the clock
- Bpulse of the processor
- Cit begins by itself
- Dboth of clock and processor pulse
- Enone of the above
133Select the correct interpretation(s) of Amdahl's Law
- Ais used to compare computers' performance
- Bis used calculate the execution time of a program
- Cis used to find the maximum expected improvement
- Dit means that it is the algorithm that decides the speedup not the number of processors
134Choose the component f SSD for the following definition\: provides SSD device level interfacing and firmware execution
- AController
- BAddressing
- CData buffer/cache
- DError correction
- EFlash memory components
135The RAID scheme consists of 7 levels
- ATrue
- BFalse
136Using this technique processor
looks ahead in the instruction code fetched from memory and predicts which groups of instructions are likely to be p ocessed next.- ABranch prediction
- BData flow analysis
- CPipelining
- DSpeculative execution
137Choose the correct answer or the following characteristics\: 1. Depend mainly on its peripherals 2. Used for a few dedicated functions 3. Usuall
used as a part of a larger system- AMicrocontroller
- BGeneral purpose microprocessor
- CAddressing
- DController
138The time interval is called a clock rate
- ATrue
- BFalse
139What does CPI stand for?
- ACycles Per Instruction
- BClocks Per Instruction
- CCycles Per Interface
- DClocks Per Interface
140Choose the correct syntax of assembly statements
- Aname operation operand(s) comments
- Boperation name operand(s) comments
- Coperation operand(s) name comments
- Dcomments name operation operand(s)
141The methods of accessing units of data
- ASequential access
- BPseudo access
- CDirect access
- DIndirect access
- ESingle access
- FRandom access
- GAssociative access
142What does LRU stand for?
- ALeast Right Used
- BLast Recently User
- CLast Recently Used
- DLeast Recently Used
143There are three types of cache addresses
- ATrue
- BFalse
144What does RAID stand for?
- ARandom Array of Independent Disks
- BRedundant Array of Independent Disks
- CRedundant Array of Interoperable Disks
- DRandom Access to Independent Disks
145There are two types of mapping functions
- ATrue
- BFalse
146Choose the correct syntax of variable declarat on in assembly
- Avariable_name type initial_value
- Btype variable_name initial_vaule
- Cvariable_name type initial_value2)
- Dtype initial_value variable_name
147The rate at which data can be transferred into or out of a memory unit is called
- ATransfer time
- BTransfer Rate
- CMIPS
- DFLOPS
- EMFLOPS
148There is no memory allocated for constants in assembly language
- ATrue
- BFalse
149Three bits make hexadecimal digit
- ATrue
- BFalse
150We can find needed block in associatively mapped cache by its block address
- ATrue
- BFalse
151Choose the definition for capacity misses
- AOccurs if the cache cannot contain all the blocks needed during execution of a program
- BThe very first access to a block cannot be in the cache
- COccurs if the block placement strategy is not fully associative
152What is time elapsed to program execution?
- ACPU Time
- BUser time + OS Time
- CI/O waiting & Other programs
- DCPU Time + I/O waiting & Other programs
153When using microprocessor based systems, it is enough to update the software
- ATrue
- BFalse
154What is the description(s) of Transistor?
- AA semiconductor device used to reduce or switch electronic signals and electrical power.
- BA semiconductor device used to amplify or switch electronic signals and electrical power.
- CA semiconductor device used to amplify electronic signals and electrical power.
- DA semiconductor device used to switch electronic signals and electrical power.
- EA semiconductor device used to reduce or combain electronic signals and electrical power.
155Choose the definition for compulsory misses
- AOccurs if the cache cannot contain all the blocks needed during execution of a program
- BOccurs if the block placement strategy is not fully associative
- CThe very first access to a block cannot be in the cache
156What is used to manage the ccess to and the use of the data and address lines?
- Aaddress bus
- Bcontrol lines
- Cmemory write
- Dbus grant
- Eaddress lines
157What kind of memory type stores data using virtual addresses\:
- ALogical
- BVirtual
- CPeripheral
- DMain
- EBuffer
158Which type of memory stores frequently used data?
- AMain Memory
- BVirtual Memory
- CAuxiliary Memory
- DSecondary Memory
- ECache Memory
159 Choose the definition for conflict misses
- AOccurs if the block placement strategy is not fully associative
- BOccurs if the cache cannot contain all the blocks needed during execution of a program
- CThe very first access to a block cannot be in the cache
160What measures the ability of a computer to complete a single task?
- AClock rate
- BSpeed metric
- CClock speed
- DClock cycle
- EExecution speed
161Choose the definition of code segment in assembly
- AContains a program's instructions
- BA block of memory to store a stack
- CAll variable definitions
162What provides storage internal to the CPU?
- ARegisters
- BArithmetic and logic unit
- CCPU interconnection
- DControl unit
163Which keyword you should use in order to define a constant in assembly language
- AEQU
- BDD
- CCONST
- DEQ
- EDW
164Choose the definition of data segment in assembly
- AAll variable definitions
- BA block of memory to store a stack
- CContains a program's instructions
165Which digits are used in octal number system?
- A0-7
- B0 and 1
- C0-9
- DAll digits
166Choose the definition of stack segment in assembly
- AA block of memory to store a stack
- BAll variable definitions
- CContains a program's instructions
167Which symbol you should use to leave the variable uninitialized
- A?
- B!
- C@
- D$
168Which keyword you sho ld use in order to define a constant in assembly language
- AEQU
- BDD
- CCONST
- DEQ
- EDW
169Choose the right formula for AMAT
- AAMAT \= Hit time + Miss rate + Miss penalty
- BAMAT \= Hit time * Miss rate + Miss penalty
- CAMAT \= Hit time * Miss rate * Miss penalty
- DAMAT \= Hit time + Miss rate * Miss penalty
170Which of the following laws d als with the potential speedup of a program using multiple processors compared to a single processor.
- AMoor's Law
- BLittle's Law
- CMurphy's law
- DAmdahl's law
171You should use a radix symbol in order to differentiate between binary, octal or hexadecimal
- ATrue
- BFalse
172Which stage is responsible f r storing and loading values to and from memory?
- AInstruction Fetch
- BMemory read/write
- CInstruction Decode
- DExecution
- EWrite Back
173Choose the years of the first generation comp
- A1958-1964
- B1964-1974
- C1974-present
- D1945-1964
- E1945-1958
174Which symbol you should use to leave the ariable uninitialized
- A?
- B!
- C@
- D$
175Which technique allows to process r simultaneously work on multiple instructions?
- ABranch prediction
- BData flow analysis
- CPipelining
- DSpeculative execution
176Choose the years of the second generation computer architecture
- A1945-1958
- B1964-1974
- C1974-present
- D1945-1964
- E1958-1964
177Following algorithms on machine with a direct-mapped data cache with 8-byte blocks. The cache is initially empty.You are given the followi
g definitions\:\n struct point_color \{\n int c,m,y,k; \}\n struct point_color square[8][8];\n int i, j;\n for (i \= 0; i < ; i++) \{\n for (j \= 0; j < 8; j++) \{\n square[i][j].c \= 0;\n square[i][j].m \= 0;\n square[i][j].y \= 1;\
square[i][j].k \= 0;\n
\}\n \n What is the total number of writes that hit in the cache?- A224
- B87
- C75
- D144
- E95
178Which technique helps to process r investigates which instructions are dependent on each other's results, or data, to create an optimized schedule of ins ructions
- ABranch prediction
- BData flow analysis
- CPipelining
- DSpeculative execution
179Clock Frequency of SDRAM is equal to
- A200
- B600
- C300
- D166
- E156
180Which type of memory stores frequently used data?
- AMain Memory
- BVirtual Memory
- CAuxiliary Memory
- DSecondary Memory
- ECache Memory
181Following algorithms on machine with a direct-mapped data cache with 8-byte blocks. The cache is initially empty.You are given the followi
g definitions\:\n struct point_color \{\n int c,m,y,k; \}\n struct point_color square[8][8];\n int i, j;\n for (i \= 0; i < ; i++) \{\n for (j \= 0; j < 8; j++) \{\n square[i][j].c \= 0;\n square[i][j].m \= 0;\n square[i][j].y \= 1;\
square[i][j].k \= 0;\n
\}\n \n What is the total number of writes that miss in the cache?- A32
- B97
- C176
- D44
- E69
182Program executes 0.125 seconds on a CPU with 4 680 000 instructions and 3 cycles per instruction. Find the clock rate of this CPU.
- A0,112 GHz
- B0,100 GHz
- C0,95 GHz
- D0,130 GHz
183How many generations se iconductor memory has been through, since 1970?
- A13
- B125
- C123
- D32
- E34
184Following algorithms on machine with a direct-mapped data cache with 8-byte blocks. You are given the following definitions\:\n struct poin _color \{\n int c,m,y,k; \}\n struct point_color square[8][8];\n int i, j;\n for (i \= 0; i < 8; i++) \{\n for (j \= 0; j <
; j++) \{\n square[i][j].c \= 0;\n square[i][j].m \= 0;\n square[i][j].y \= 1;\n square[i][j].k \= 0;\n \}\n What is the miss rate?{- A32
- B25
- C12,5%
- D128
185Contains a word to be stored i
memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit- AMemory buffer register (MBR)
- BMemory address register (MAR)
- CInstruction register (IR)
- DInstruction buffer register (IBR)
- EProgram counter (PC)
186Microprocessor can't do all the fu ctions of a computer system on its own
- ATRUE
- BFALSE
187A technique used in adv nced microprocessors where the microprocessor begins executing a first instruction before the second has been com leted is called pipelining
- ATrue
- BFalse
188Contains the 8-bit opcode instruction being executed
- AInstruction register (IR)
- BMemory buffer register (MBR)
- CMemory address register (MAR)
- DInstruction buffer register (IBR)
- EProgram counter (PC)
189Total instruction count 3 750 000 instructions
Average CPI 2,5 cycles per instruction
Clock rate 900 MHz
Calculate the execution time of program running on this CPU.- A0,002
- B0,010
- C0,024
- D0,103
- E0,119
190After implementing embedde
systems, you can easily use them for another purposes- ATrue
- BFalse
191Following algorithms on machine with a direct-mapped data cache with 8-byte blocks. You are given the following definitions\:\n struct poin _color \{\n int c,m,y,k; \}\n struct point_color square[8][8];\n int i, j;\n for (i \= 0; i < 8; i++) \{\n for (j \= 0; j <
; j++) \{\n square[i][j].c \= 0;\n square[i][j].m \= 0;\n square[i][j].y \= 1;\n square[i][j].k \= 0;\n \}\n What is the hit rate?{- A224
- B32
- C12,5%
- D87,5%
192Controls the operation of the co puter and performs its data processing functions
- AMain memory
- BI/O
- CCPU
- DSystem interconnection
193An instruction may have one or more operands
- ATrue
- BFalse
194Digital circuits are inflexible and sl wer, because they are technology dependent
- ATrue
- BFalse
195Following algorithms on machine with a direct-mapped data cache with 8-byte blocks. The cache is initially empty. You are given the follow
ng definitions\:\n struct point_color \{\n int c,m,y,k; \}\n struct point_color square[8][8];\n int i, j;\n for (i \= 0; i < 8; i++) \{\n for (j \= 0; j < 8; j++) \{\n square[j][i].c \= 0;\n square[j][i].m \= 0;\n square[j][i].y \= 1;\n square[j][i].k \= ;\n \}\n \n What is the total number of writes that miss in the cache?{- A64
- B78
- C125
- D76
196CPU Time \= I * CPI / R. hich parameter requires special profiling software?
- ACycles Per instruction
- BClock Rate
- CNumbers of instructions
- DExecution time
197Four bits make octal digit
- ATrue
- BFalse
198Total instruction count 3 250 000 instructions
Average CPI 1.7 cycles per instruction
Clock rate 500 MHz
Calculate the execution time of program running on this CPU.- A0,00231
- B0,01105
- C0,01204
- D0,10203
199Following algorithms on machine with a direct-mapped data cache with 8-byte blocks. The cache is initially empty. You are given the follow
ng definitions\:\n struct point_color \{\n int c,m,y,k; \}\n struct point_color square[8][8];\n int i, j;\n for (i \= 0; i < 8; i++) \{\n for (j \= 0; j < 8; j++) \{\n square[j][i].c \= 0;\n square[j][i].m \= 0;\n square[j][i].y \= 1;\n square[j][i].k \= ;\n \}\n \n What is the total number of writes that hit in the cache?{- A192
- B78
- C125
- D76
200IBM System/360 Model 91 was introduced in 1966
- ATrue
- BFalse
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- Description
- Quiz on CSA GOS 1, created by Bauyrzhan Zivadinov on 27/04/2020.
- Author
- Bauyrzhan Zivadinov
- Language
- English
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