Quiz
[CPSC313 Final] Focus Quiz Unit 2
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Questions in this quiz (25)
1Consider the variables a and b. A causal dependency is defined as A<B (Instruction A immediately precedes B) if
- AB reads value written by A
Example:
a = 1;
b = a; - BB write to visible location written by A
Example:
a = 1;
a = 2; - CB write to a location read by A
Example:
b = a;
a = 1;
- AB reads value written by A
2Consider the variables a and b. An anti dependency is defined as A<B (Instruction A immediately precedes B) if
- AB write to a location read by A
Example:
b = a;
a = 1; - BB reads value written by A
Example:
a = 1;
b = a; - CB write to visible location written by A
Example:
a = 1;
a = 2;
- AB write to a location read by A
3To prevent a data hazard by stalling, we can
- Aread registers in decode that are written by instructions in E, M, or W and then stall the instruction in decode until writer is retired
- Bread registers in fetch that are written by instructions in E, M, or W and then stall the instruction in fetch until writer is retired
- Cread registers in execute that are written by instructions in E, M, or W and then stall the instruction in execute until writer is retired
4How would we resolve a conditional jump control hazard by stalling?
- Astall fetch until jump exits execute
- Bstall execute until jump exits decode
- Cstall fetch and execute until jump exits decode
- Dstall fetch, decode, and execute until jump exits memory
- Estall fetch, decode, execute, and memory until jump exits write back
- Fjust stall everything after fetch indefinitely and go finish off a bottle of wine in one go
5How would we resolve a return control hazard by stalling?
- Astall fetch until return exits memory
- Bstall decode until return exits memory
- Cstall fetch and decode until return exits memory
- Dstall fetch, decode, and execute until return exits memory
- Estall fetch, decode, execute, and memory until return exits memory
- Freturn to cpsc313 in the summer after you fail this midterm
6How would we handle a load-use hazard?
- AStall use one cycle, forward to D from M or W
- BStall use one cycle, forward to D from E or M
- CStall use one cycle, forward to E from D, M, or W
- DStall use one cycle, forward to E from M or W
7valC is the address for the jump as if it were [blank_start]not taken[blank_end] and valP is the address for the jump as if it were [blank_start]taken[blank_end].
- Anot taken
- Btaken
8When a mis-predicted jump is in M, what should we do?
- Ashootdown D and E to prevent them from doing damage
- Bshootdown F and D to prevent them from doing damage
- Cshootdown M and W to prevent them from doing damage
9Which of these are attributes of super-scalar?
- Amultiple pipelines that run in parallel
- Bissue multiple instructions on each cycle
- Cinstructions execute in parallel and can even bypass each other
- Dif I shut my eyes tight enough, will the midterm disappear?
10What does hyper-threading consist of? (Only one of the following is correct)
- AOS loads multiple runnable threads into CPU, usually from the same process
- BCPU does fast switching between threads to hide memory latency
11In a pipelined processor, if you measure the total propagational delay (including stage-memory overhead) of every stage, what have you measured?
- AClock rate
- BThroughput
- CLatency
- DClock period
- ENone of the above
12
Which of the following statements is true about the following two instructions when executed in sequence (i.e., one right after the other) in the 5-stage, Y86 pipeline we have discussed in class.
addl %ebx, %ecx # R[ecx] <= R[ebx] + R[ecx]; setting condiition codes
addl %eax, %ebx # R[ebx] <= R[eax] + R[ebx]; setting condition codes- AThere is a dependency between the two instructions but there is no pipeline hazard.
- BThere is a dependency between the two instructions and there is a pipeline hazard.
- CThere is no dependency between the two instructions but there is a pipeline hazard.
- DThere is neither a dependency between the two instructions nor is there a pipeline hazard.
13
Which of the following statements is true about the following two instructions when executed in sequence (i.e., one right after the other) in the 5-stage, Y86 pipeline we have discussed in class.
movl %eax, (%ebx) # M[R[ebx]] <= R[eax]; not setting condition codes
movl (%ebx), %ecx # R[ecx] <= M[R[ebx]]; not setting condition codes- AThere is a dependency between the two instructions but there is no pipeline hazard.
- BThere is a dependency between the two instructions and there is a pipeline hazard.
- CThere is no dependency between the two instructions but there is a pipeline hazard.
- DThere is neither a dependency between the two instructions nor is there a pipeline hazard.
14
Which of the following statements is true about the following two instructions when executed in sequence (i.e., one right after the other) in the 5-stage, Y86 pipeline we have discussed in class.
addl %eax, %ebx # R[ebx] <= R[eax] + R[ebx]; setting condition codes
jne foo # jump to foo if and only if condition codes indicate last ALU result was not equal to zero- AThere is a dependency between the two instructions and there is a pipeline hazard.
- BThere is a dependency between the two instructions but there is no pipeline hazard.
- CThere is no dependency between the two instructions but there is a pipeline hazard.
- DThere is neither a dependency between the two instructions noris there a pipeline hazard.
15
Which of the following statements is true about the following two instructions when executed in sequence (i.e., one right after the other) in the 5-stage, Y86 pipeline we have discussed in class.
addl %eax, %ebx # R[ebx] <= R[eax] + R[ebx]; setting condition codes
jmp foo # jump to foo- AThere is neither a dependency between the two instructions nor is there a pipeline hazard.
- BThere is a dependency between the two instructions and there is a pipeline hazard.
- CThere is a dependency between the two instructions but there is no pipeline hazard.
- DThere is no dependency between the two instructions but there is a pipeline hazard.
16Which statement best describes how Y86 PIPE handles access to %eax in this sequence of instructions?
addl %ebx, %eax # R[eax] <= R[ebx] + R[eax]
addl %esi, %edi # [Redi] <= R[esi] + R[edi]
rmmovl %eax, (%ecx) # M[R[ecx]] <= R[eax]- AForward from M to D with no stall.
- BForward from E to D with no stall
- CForward from E to D with one stall.
- DForward from M to D with one stall.
- EForwarding between two other stages (or in a different order) with no stall.
- FForwarding between two other stages (or in a different order) with one stall.
- GForwarding is not possible.
- HNone of the above.
17
Which statement best describes how Y86 PIPE handles access to %eax in this sequence of instructions?
mrmovl (%ebx), %eax # R[eax] <= M[R[ebx]]
addl %esi, %edi # [Redi] <= R[esi] + R[edi]
rmmovl %eax, (%ecx) # M[R[ecx]] <= R[eax]- AForward from M to D with no stall.
- BForward from E to D with no stall
- CForward from E to D with one stall.
- DForward from M to D with one stall.
- EForwarding between two other stages (or in a different order) with no stall.
- FForwarding between two other stages (or in a different order) with one stall.
- GForwarding is not possible.
- HNone of the above.
18
Which statement best describes how Y86 PIPE handles access to %eax in this sequence of instructions?
mrmovl (%ebx), %eax # R[eax] <= M[R[ebx]]
addl %esi, %edi # [Redi] <= R[esi] + R[edi]
addl %esp, %ebp # R[ebp] <= R[esp] + R[ebp]
rmmovl %eax, (%ecx) # M[R[ecx]] <= R[eax]- AForwarding between two other stages (or in a different order) with no stall.
- BForward from E to D with no stall
- CForward from E to D with one stall.
- DForward from M to D with no stall.
- EForward from M to D with one stall.
- FForwarding between two other stages (or in a different order) with one stall.
- GForwarding is not possible.
- HNone of the above.
19Which of the following statements best describes how Y86 pipe handles conditional jumps.
- AIt predicts that the jump is taken when it is in D and if it later determines that the jump was not taken, it (1) bubbles D and E when the jump is in E and (2) selects a new PC value for F when the jump is in M.
- BIt determines whether the jump is taken when the jump is in D.
- CIt predicts that the jump is not taken when it is in D and if it later determines that the jump was taken, it (1) bubbles D and E when the jump is in E and (2) selects a new PC value for F when the jump is in M.
- DIt predicts that the jump is taken when it is in D and if it later determines that the jump was not taken, it (1) bubbles D and E when the jump is in E and (2) selects a new PC value for F when the jump is in E.
- EIt predicts that the jump is not taken when it is in D and if it later determines that the jump was taken, it (1) bubbles D and E when the jump is in E and (2) selects a new PC value for F when the jump is in E.
- FIt predicts that the jump is taken when it is in D and if it later determines that the jump was not taken, it (1) bubbles D and E when the jump is in M and (2) selects a new PC value for F when the jump is in M.
- GIt predicts that the jump is not taken when it is in D and if it later determines that the jump was taken, it (1) bubbles D and E when the jump is in M and (2) selects a new PC value for F when the jump is in M.
- HNone of the above.
20The implementation of jump (branch) prediction involves two circuits named "Select PC" and "Predict PC". "Select PC" reads F.prPC and sets f.pc and "Predict PC" sets f.prPC. Which statement bests describes the relationship between these two circuits.
- A"Predict PC" and "Select PC" can procede in parallel beacuse the value computed by "Predict PC" in cycle i is not used in cycle i by "Select PC.
- B"Predict PC" must complete its computation before "Select PC" can begin, because the output of "Predict PC" is the input to "Select PC".
- C"Predict PC" and "Select PC" can procede in parallel, but the clock period must be long enough so that "Select PC"'s output reflects the prPC value computed by "Predict PC" in that cycle.
- D"Predict PC" and "Select PC" can proceded in parallel because the value computed by "Predict PC" can be sent to "Select PC" via data fowarding.
21Comparing static and dynamic jump prediction, which statement best describes the advantage (if any) the compiler has over the pipeline.
- AThe pipeline is better at examining the dynamic nature of the program, but this information is not aways as useful as information the compiler can gather and so both should be involved, but priority should be given to the compiler.
- BThe compiler can spend more time analyzing a program and so can more easily determine which portions of code are more likely to be executed by examining the dynamic nature of the program (e.g., in if statements).
- CThe compiler sees more of the program at once compared to the pipeline and so can more easily determine whether jumps will normally be taken by examining the only static structure of the program; dynamic information is not useful for jump prediction.
- DThe pipeline is better at examining the dynamic nature of the program and this information is typically more useful than information the compiler can gather and so both can be involved, but priority should be given to the pipeline.
22Consider what (if anything) should be specified in the instruction set architecure (ISA) about how a processor implementation should handle jump prediction.
- AThe ISA should specify that jumps are normally taken but that dynamic information can be used to predict a jump is not taken if and only if recently history of that jump indicates that it was mostly not taken.
- BThe ISA should not specify anything; it should instead give hardware implementations the flexibility to implement jump prediction in best way permitted by current technology.
- CThe ISA should specify that all jumps must be predicted taken.
- DThe ISA should specify that a jump is taken but that dynamic information can be used to predict that a jump is not taken and that this prediction should be kept simple; for example, it would be permissible to predict a jump is not taken if it was not taken the last time it executed.
23What type of parallism (if any) are super-scalar architectures designed to exploit?
- Ainstruction-level parallism
- Bthread-level parallism
- Cboth
- Dneither
24The access-latency difference between the register file and main memory is roughly the same magnitude as the difference between main memory and disks (i.e.,hard drives).
- ATrue
- BFalse
25Which of the following statements best describes the relationship between the register file and the L1 cache?
- AThey have roughly the same access latency but instructions that access the register file are smaller than instructions that access the L1 cache.
- BThe register file is much faster (i.e. has lower access latency) and instructions that access it are the same size as instructions that access the L1 cache.
- CThe register file is much faster and instructions that access it are smaller than instructions that access the L1 cache.
- DThey have roughly the same access latency and instructions that access the register file are the same size as instructions that access the L1 cache.
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- CS313 Quiz on [CPSC313 Final] Focus Quiz Unit 2, created by Zim Brightwood on 10/12/2016.
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- Zim Brightwood
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