Karteikarten
Clock Skew / CTS
Karten in diesem Stapel (15)
- 1What are the main causes of clock skew?Differences in interconnect wire lengths, variations in wire parasitics, or inductive coupling from neighboring wires.
Also Process, Voltage, and Temperature (PVT) changes or material defects. - 2Define positive and negative skew.Positive Skew:
Capture Flop Delay > Launch Flop Delay
Negative Skew:
Launch Flop Delay > Capture Flop Delay - 3Describe how Positive Skew affects Setup and Hold Times.Setup:
- More time for data to travel
- Push higher operating frequency
- Easier to meet setup constraints
Hold:
- Input data must be held stable longer
- Harder to meet hold constraints - 4Describe how Negative Skew affects Setup and Hold Times.Setup:
- Less time for data to travel
- Harder to meet setup constraints
Hold:
- Reduces time input data needs to be stable
- Easier to meet hold constraints - 5What is the High-Level goal of Clock Tree Synthesis (CTS)?Implement a hierarchical clock tree that distributes the clock signal to all sequential elements across the design such that clock skew is minimized to help meet setup and hold time requirements
- 6How does CTS reduce skew?• Buffers and inverters of various drives strengths are strategically inserted along the clock paths.
• These components help balance delays, compensate for parasitic effects, and align clock arrival times across the circuit.
• There are specifically designed clock buffer cells available in the standard cell library for this purpose. - 7Define Clock Jitter and its main causes.- Random variations in the arrival times of clock edges at different flip-flops, relative to an ideal reference.
- Caused by noise, power supply fluctuations, and other sources of instability in the clock generation or distribution network. - 8How is Clock Jitter minimized?Phase-Locked Loops (PLLs) and Delay-Locked Loops (DLLs)
- 9Define Global Clock Skew.The maximum value of clock skew between pairs of clock sinks.
In other words, the difference between the longest and shortest delay paths in the clock distribution network. - 10Describe Symmetric Tree Architecture.- Clock is first routed to a central point in the chip
- From the central point another symmetric architecture forks out
- Example: H-Tree or X- Tree
- This ensures that each path is balanced
- Skew is still observed due to PVT variations - 11How can skew due to PVT variations in a Symmetric Tree Architecture be mitigated?- Crosslinking can reduce PVT variation impacts.
- By creating a shared signal path, the PVT effects on the two paths become correlated. - 12When can clock skews be useful?If a significant difference in the slack exists on the two sides of a flip-flop.
- 13How can clock skews be used to improve performance?Allocate the excess margin on one side of the flip-flop to the more critical path. Thus, providing more time for data to propagate on the critical path.
- 14Name ONE additional benefit of useful clock skews aside from helping to meet timing requirements.Registers do NOT switch at the same time, therefore simultaneous current draw is less; Reducing Voltage Drop Problems.
- 15Define Clock Gating.Logic gates are added to the clock distribution tree, so portions of the tree can be turned of when not in use to save power.
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- Digital Design Karteikarten am Clock Skew / CTS, erstellt von Bryce Reid am 22/06/2026.
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- Bryce Reid
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