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Digital Design Flashcards
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- 1What are the 7 stages of ASIC Design Flow?1. Chip Specification: Microarchitecture, specifications, functionalities, and features are defined.
2. Functional Verification: Runs simulation at the design level and checks the functionality of the circuit.
3. RTL Block Synthesis: Translate RTL code into gate-level netlist by logical synthesis under the constraints.
4. Partitioning of the chip: The chip is partitioned into numerous functional blocks all linked to each other in a hierarchical order in a way such that the chip is energy efficient, occupies a small area, and is not expensive.
5. Floor Planning: It is the blueprint of the physical implementation of the chip.
6. Clock Tree Synthesis: Setting up the clock tree and consulting the predefined timing, power requirements, and area.
7. Final Verification: The final step of physical verification is just to check if there are any errors in the circuit. - 2Define Logic SynthesisThe process of translating RTL code into a gate-level digital logic implementation using cells from a target technology library.
- 3What are the 5 Goals of Logic Synthesis?1. Minimize the size of the logic gate cell count and cell size.
2. Minimize power while switching between gates.
3. Maximize performance in terms of clock performance of synchronous systems and throughput for asynchronous.
4. Quickly produce accurate Functional models.
5. Produce predictable and accurate results in timing, area, and power consumption calculations. Should correspond with the actual values measured on the physical device once manufactured. - 4What are the 8 steps of Logic Synthesis Flow?1. Syntax Analysis: Takes input of HDL files and checks for syntax errors.
2. Library Definition: Provides and allocates standard cells and IP libraries.
3. Elaboration and Binding: Translates RTL into Boolean structure. Binds all cells and makes libraries available.
4. Constraint Definition: For building a customized and specific chip, we need to define constraints according to which the chip will function. For example, clock frequency, power efficiency, etc.
5. Pre-Mapping Optimization: It performs mapping to generic cells in the library.
6. Technology Mapping: Performs mapping of the generic libraries to technology libraries.
7. Post-Mapping Optimization: Changes gate designs to meet constraints.
8. Report and Export: Give out the end results with reports on timings and export. - 5Define Synthesis and SimulationSynthesis: Translate the HDL design specification into a physical circuit implementation. Could be a programming file for an FPGA, or a specification for an integrated circuit (IC).
Simulation: The design specification is exercised to verify correct operation. Apply stimuli and observe the outputs. This is referred to as verification. Great tools for debugging. - 6Define the difference between Moore and Mealy State MachinesMoore: Outputs depend only on the current state. Easy to meet setup/hold timing requirements as states will only change on clock edges.
Mealy: Output depends on current state as well as the circuit inputs. Output reacts quickly (delayed by propagation delays) to any changes in the inputs. - 7Define the 3 steps to design a state machine1. Identify the inputs and the outputs of the system.
2. Identify the states that are required to implement the state machine.
3. Determine the conditions that will cause the state transitions. - 8What are the 6 advantages of using an HDL?- - Can implement more complex design in a short amount of time
- Software can optimize large amounts of logic better than humans
- HDLs are closer to human language and reasoning and easier for humans to write and interpret.
- Can run more complex simulations and automatically check success
- Scalable
- Code re-use is easier - 9What is a packed array?A packed array is guaranteed to
be represented as a contiguous set of bits in simulation and synthesis. - 10What is the difference between blocking and non-blocking assignments?blocking assignments (ie. y = a;) are executed before the execution the statements that
follow in a sequence of statements.
non-blocking assignments (ie. y <= a;) assign the value after all statements are
executed. - 11Name 4 advantages of Simulation Testing.1. Can catch edge cases that may be very difficult to generate in hardware.
2. Faster compilation, versus synthesis and programming. Faster turnaround time after hardware changes.
3. Cheaper, no need for hardware.
4. Easier to find errors by inspecting internal signal values. - 12Name 4 advantages of Hardware Testing.1. Can interface to real hardware to ensure real world functionality.
2. Includes timing information that simulation may not account for.
3. Can operate "at speed" which is typically much faster than simulation and can execute more test sequences.
4. Simulation results may not match the final hardware when poor coding practices are used. - 13What is the largest source of up-front costs in ASIC design?Creating the mask set is a very high NRE (Non-Recurring Engineering) cost.
- 14Name 4 possible ASIC Manufacturing Faults.1. Improper Doping
2. Mask Contamination (ie. dust, etc)
3. Defects in Silicon Structure
4. Mask Alignment Issues - 15Name 5 types of potential Electrical Defects caused by Manufacturing Faults.1. Short Circuits
2. Open Circuits
3. Stuck-On Transistors (S-A-1)
4. Stuck-Off Transistors (S-A-0)
5. Threshold Voltage Shift - 16What is the Key Benefit of New Technology Generations?Performance per Watt
- 17What is the relationship between Minimum Feature Size, Gate Capacitance, Transistor Power and Speed?As Minimum Feature Size is REDUCED
Gate Capacitance is REDUCED
Transistor Power and Speed is IMPROVED
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- Digital Design Karteikarten am Digital Design Flashcards, erstellt von Bryce Reid am 16/05/2026.
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