Quiz
CPSC313 Midterm Sample
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Questions in this quiz (31)
11a) The classic RISC pipeline consists of 5 stages, what are they?
- AFetch, Decode, Execute, Memory, Write back
- BFetch, Register, Execute, Memory, Write back
- CLoad, Register, Execute, Memory, Write-read
- DFetch, Register, Execute, Memory, Load-use
- ELoad, Register, Execute, Memory, Control
21b) Fetch is responsible for which actions? Check all that apply.
- AUse pc to read next instruction from memory into instruction register
- BDetermine instruction length and extract pieces of instruction
- CAdvance the pc to the address of next instruction in sequence
- DRead values from register file
- EUpdate the pc for taken jump instructions
31c) Which of the following is a decode action?
- Aread values from register
- Bdetermine instruction length and extract pieces of instruction
- Caccess main memory
- Ddecode the difficulty of this course into a binary representation of tears and not tears
41d) Which of the following is an execute stage action?
- Aperform ALU operations and determine whether jumps are taken
- Bset the pc for taken jumps
- Caccess main memory
- Dcry profusely into a bowl of alphabits hoping they'll arrange themselves into the proper values for the next stage
51e) Which of the following is a memory stage action?
- Aaccess main memory, duhhhhhhhhhh
- Baccess main memory and write the values back to the register file, duhhhhhhhhhhh
- Cwhen in doubt choose c
- Dadvance the pc to the next memory address in the sequence
61f) Which of the following is a write back stage action?
- Awrite values back to register file
- Bwrite values back to main memory
- Cwrite values back to the pc
- Dforge your computer science degree when failing this course leads you into months of crippling depression
72a) Why is the memory stage after the execute stage? Include a Y86 instruction that could not be implemented if you reversed the order.
- AExecute needs to perform address calculations. mrmovl could not use base plus displacement addressing
- BExecute needs to perform math on register values. None of the op instructions would work (i.e. addl)
- CMemory needs to write a value from memory into a register. mrmovl would not work if the order was reversed.
- DMemory needs to read from memory in order for execute to work properly. ret would not work if the order was reversed.
82b) Why is the execute stage after the decode stage? Include a Y86 instruction that could not be implemented if you reversed the order.
- AExecute needs to be able to perform math on register values. If the order were reversed, none of the op instructions would work (i.e. addl)
- BExecute needs to perform address calculations. If the order were reversed, mrmovl would not work.
- CDecode needs to write a value from memory into a register. mrmovl would no longer work if the order was reversed.
- DDecode needs to read the values before execute stage to avoid stalling. popl would no longer work if the order was reversed.
92c) Why is the write-back stage after the memory stage? Include a Y86 instruction that could not be implemented if you reversed the order.
- AMemory needs to perform math on memory values. In the reverse order, none of the op instructions would work (i.e. addl)
- BMemory needs to perform address calculations. In the reverse order, mrmovl and rmmovl would not work.
- CWrite back needs to be able to write a value from memory into a register. In the reverse order, mrmovl would not work.
103a) RISC instruction sets do not allow ALU operations to read from memory. Explain how the structure of the pipeline leads this restriction.
- ASince M comes after E, by the time we read the value from memory, it's too late.
- BSince M comes before E, by the time we read the value from memory, it's too late.
- CSince E comes after M, by the time we read the value from memory, it's too late.
113b) Describe how the pipeline could be modified to lift this restriction. You may not change the number
of pipeline stages or their basic function. Your revised pipeline does not need to be able to implement
every Y86 instruction (in fact it would not be able to) but it must be able to execute instructions like:
addl (%eax), %ebx # r[ebx] = r[ebx] + m[r[eax]]- ASwap the order of E and M
- BAllow for M to forward data back to E
- CStall E until M has the correct data
123c) This revised pipeline must place some restrictions on the revised ISA that it implements. One of
the impacts is on mrmovl and rmmovl. Describe the problem and modify the instructions so that
they will work with the new pipeline. Note that the revised versions need not be as powerful as the
original ones, but they must still load and store between memory and a register.- AWe wouldn't be able to handle base plus addressing because E would come after M. To solve this, we simply eliminate base plus addressing
- BMemory access is rendered useless. To solve this, we simply eliminate the memory stage.
- CThe write back stage would no longer be able to determine the correct register to move data to. To solve this, we would simply add another stage input to account for that lost addressing.
13Consider the following five-stage pipeline with stage delays (including overheads) of 34 ps,
42 ps, 75 ps, 50 ps and 18 ps.
What is the maximum clock rate (i.e., fastest) acceptable for this pipeline?
[blank_start]1 cycle / 75ps = 1000/75 Ghz[blank_end]- A1 cycle / 75ps = 1000/75 Ghz
- B1 cycle / 34ps = 1000/34 Ghz
- C1 cycle / 42ps = 1000/42 Ghz
- D1 cycle / 50ps = 1000/50 Ghz
- E1 cycle / 18ps = 1000/18 Ghz
14Consider the following five-stage pipeline with stage delays (including overheads) of 34 ps,
42 ps, 75 ps, 50 ps and 18 ps.
What is the maximum throughput of this pipeline?
[blank_start]1/75 instructions per picosecond[blank_end]- A1/75 instructions per picosecond
- B1/34 instructions per picosecond
- C1/42 instructions per picosecond
- D1/50 instructions per picosecond
- E1/18 instructions per picosecond
154c) Consider the following five-stage pipeline with stage delays (including overheads) of 34 ps,
42 ps, 75 ps, 50 ps and 18 ps.
What, if anything, might cause the actual throughput of programs to be lower than this maximum?- Apipeline bubbles
- Bnothing would cause that, the maximum is actually also the minimum
- Cjumps and returns
- Dstack depletion
16Consider the following five-stage pipeline with stage delays (including overheads) of 34 ps,
42 ps, 75 ps, 50 ps and 18 ps.
What is the minimum instructions latency of this pipeline?
[blank_start]75ps + 75ps + 75ps + 75ps + 75ps[blank_end]- A75ps + 75ps + 75ps + 75ps + 75ps
- B34ps + 42ps + 50ps + 75ps + 18ps
- C18ps + 18ps + 18ps + 18ps + 18ps
175a) Consider the following piece of Y86 assembly code:
[0] addl %eax, %ebx
[1] irmovl $1, %eax
[2] mrmovl %(ebx), %ebx
[3] addl %ebx, %eax
List all of the output dependencies present in this code.- A0 and 2 on %ebx
- B0 and 1 on %eax
- C0 and 3 on %ebx
- D1 and 2 on %ebx
- E1 and 3 on %eax
- F2 and 3 on %ebx
185a) Consider the following piece of Y86 assembly code:
[0] addl %eax, %ebx
[1] irmovl $1, %eax
[2] mrmovl %(ebx), %ebx
[3] addl %ebx, %eax
List all of the anti dependencies present in this code.- A0 and 1 on %eax
- B0 and 2 on %ebx
- C0 and 3 on %ebx
- D1 and 2 on %ebx
- E1 and 3 on %eax
- F2 and 3 on %ebx
195a) Consider the following piece of Y86 assembly code:
[0] addl %eax, %ebx
[1] irmovl $1, %eax
[2] mrmovl %(ebx), %ebx
[3] addl %ebx, %eax
List all of the causal dependencies present in this code.- A0 and 1 on %eax
- B0 and 2 on %ebx
- C0 and 3 on %eax
- D1 and 2 on %ebx
- E1 and 3 on %eax
- F2 and 3 on %ebx
205b) Consider the following piece of Y86 assembly code:
[0] addl %eax, %ebx
[1] irmovl $1, %eax
[2] mrmovl %(ebx), %ebx
[3] addl %ebx, %eax
List all of the data hazards present in this code for the Y86, five stage pipeline- AAll the dependencies
- BAll the causal dependencies
- CAll the output dependencies
- DAll the anti dependencies
- EJust the causal and output dependencies
- FJust the causal and anti dependencies
- GJust the anti and output dependencies
215c) Consider the following piece of Y86 assembly code:
[0] addl %eax, %ebx
[1] irmovl $1, %eax
[2] mrmovl %(ebx), %ebx
[3] addl %ebx, %eax
For each hazard, indicate the total number of bubbles added by the Pipe-Minus implementation- A2 for dependency between 0 and 2 on %ebx
- B1 for dependency between 0 and 2 on %ebx
- C3 for dependency between 0 and 2 on %ebx
- D0 for dependency between 1 and 3 on %eax
- E1 for dependency between 1 and 3 on %eax
- F2 for dependency between 1 and 3 on %eax
- G0 for dependency between 0 and 2 on %ebx
- H3 for dependency between 1 and 3 on %eax
- I3 for dependency between 2 and 3 on %ebx
- J2 for dependency between 2 and 3 on %ebx
225d) Consider the following piece of Y86 assembly code:
[0] addl %eax, %ebx
[1] irmovl $1, %eax
[2] mrmovl %(ebx), %ebx
[3] addl %ebx, %eax
For each hazard, indicate the total number of bubbles added by the Pipe implementation- A1 for dependency between 2 and 3 on %ebx
- B2 for dependency between 2 and 3 on %ebx
- C3 for dependency between 2 and 3 on %ebx
- D0 for dependency between 2 and 3 on %ebx
23Describe the implementation of the following new instruction for Y86 Seq as you did in
Homework 2. This instruction is similar to mrmovl except that it adds 4 to rB and does not have a static-displacement operand. It would be useful, for example, for iterating over an array of integers.
Syntax:
mrmovincl (rB), rA
Semantics:
r[rA] <= m[r[rB]]
r[rB] <= r[rB] + 4
Memory Layout:
| 5 | F | rA | rB |
Describe each stage using a relaxed syntax similar as shown below. The Fetch and PC Update stages are complete. List only the code that would be added for this instruction.
Fetch:
f.iCd = m[F.pc] >> 4
f.iFn = m[F.pc] & 0xf
f.rA = m[F.pc+1] >> 4
f.rB = m[F.pc+1] & 0xf
f.valP = F.pc + 2
Decode:
d.srcA = [blank_start]R_NONE[blank_end]
d.srcB = [blank_start]D.rB[blank_end]
d.dstE = D.rB
d.dstM = [blank_start]D.rA[blank_end]
d.valB = [blank_start]r[d.srcB][blank_end]
Execute:
e.aluA = 4
e.aluB = [blank_start]E.valB[blank_end]
e.aluFun = [blank_start]A_ADD[blank_end]
e.valE = [blank_start]4 + E.valB[blank_end]
Memory:
m.valM = [blank_start]m4[M.valB][blank_end]
Write Back:
r[W.dstE] = [blank_start]W.valE[blank_end]
r[W.dstM] = [blank_start]W.valM[blank_end]
PC Update (pseudo stage):
w.pc = W.valP- AR_NONE
- BD.rB
- CD.rA
- Dr[d.srcB]
- EE.valB
- FA_ADD
- GA_SUB
- HA_INC
- I4 + E.valB
- Jm4[M.valB]
- Km4[M.srcB]
- LW.valE
- MW.valM
- NR_ADD
- OR_SUB
24Write Y86 assembly code that computes the sum of an array of integers where the address of
the array is stored in %ebx and the length of the array is in %ecx. Place the sum in %eax.
irmovl $0, [blank_start]%eax[blank_end] #SET SUM TO 0
irmovl $[blank_start]1[blank_end], %edi #HOW MUCH WILL THE LENGTH DECREMENT BY AS YOU ITERATE?
irmovl $[blank_start]4[blank_end], %esi #AN ARRAY OF INTEGERS HAS ELEMENTS WITH A SIZE OF?
[blank_start]andl[blank_end] %ecx, %ecx #IS THE LENGTH OF THE ARRAY 0?
jle L1
L0: [blank_start]mrmovl[blank_end] [blank_start](%ebx)[blank_end], %edx #STORE ADDRESS OF ARRAY INTO %edx
addl [blank_start]%edx[blank_end], %eax #ADD VALUE OF ELEMENT IN THE ARRAY TO SUM
addl [blank_start]%esi[blank_end], %ebx #INCREMENT THE ARRAY POINTER
subl [blank_start]%edi[blank_end], %ecx #DECREMENT THE LENGTH OF THE ARRAY
[blank_start]jg[blank_end] L0 #CHECK IF LENGTH IS STILL GREATER THAN ZERO
L1:- A%eax
- B1
- C2
- D3
- E4
- F5
- Gandl
- Hmrmovl
- Irmmovl
- Jrrmovl
- K(%ebx)
- L%ebx
- M%edx
- N%esi
- O%edi
- Pjg
- Qjge
- Rjle
- Sjl
258a) What is spatial locality and why is it important?
- ASpatial locality exists when memory accesses are clustered together to nearby memory addresses
- BCaches exploit spatial locality by storing data in multi-byte blocks.
- CSpatial locality exists when the same memory location is accessed repeatedly.
- DCaches exploit spatial locality by retaining recently accessed blocks in the cache.
- ESpatial locality exists between a pair of instructions when there are no dependencies between them and thus their execution order does not matter.
- FPipelined (and super-scalar) processor architectures exploit spatial locality.
- GSpatial locality exists when programs explicitly indicate that threads of execution can be executed in parallel by either directly or indirectly creating multiple threads that can execute con-currently.
- HMulti-core processors (and hyper-threading) exploit spatial locality.
268b) What is temporal locality and why is it important?
- ATemporal locality exists when memory accesses are clustered together to nearby memory addresses.
- BCaches exploit temporal locality by storing data in multi-byte blocks.
- CTemporal locality exists when the same memory location is accessed repeatedly.
- DCaches exploit temporal locality by retaining recently accessed blocks in the cache.
- ETemporal locality exists between a pair of instructions when there are no dependencies between them and thus their execution order does not matter.
- FPipelined (and super-scalar) processor architectures exploit temporal locality.
- GTemporal locality exists when programs explicitly indicate that threads of execution can be executed in parallel by either directly or indirectly creating multiple threads that can execute con-currently.
- HMulti-core processors (and hyper-threading) exploit temporal locality.
278c) What is instruction-level parallelism and why is it important?
- AInstruction-level parallelism exists between a pair of instructions when there are no dependencies
between them and thus their execution order does not matter. - BPipelined (and super-scalar) processor architectures exploit instruction-level parallelism.
- CInstruction-level parallelism exists when programs explicitly indicate that threads of execution can be executed in parallel by either directly or indirectly creating multiple threads that can execute con-currently.
- DMulti-core processors (and hyper-threading) exploit instruction-level parallelism.
- EInstruction-level parallelism exists when the same memory location is accessed repeatedly.
- FCaches exploit instruction-level parallelism by storing data in multi-byte blocks.
- GInstruction-level parallelism exists when memory accesses are clustered together to nearby memory addresses.
- HCaches exploit instruction-level paralellism by retaining recently accessed blocks in the cache.
- AInstruction-level parallelism exists between a pair of instructions when there are no dependencies
288d) What is thread-level parallelism and why is it important?
- AThread-level parallelism exists when programs explicitly indicate that threads of execution can be executed in parallel by either directly or indirectly creating multiple threads that can execute con-currently.
- BMulti-core processors (and hyper-threading) exploit thread-level parallelism.
- CThread-level parallelism exists between a pair of instructions when there are no dependencies
between them and thus their execution order does not matter. - DPipelined (and super-scalar) processor architectures exploit thread-level parallelism.
- EThread-level parallelism exists when the same memory location is accessed repeatedly.
- FCaches exploit thread-level parallelism by retaining recently accessed blocks in the cache.
- GCaches exploit thread-level parallelism by storing data in multi-byte blocks.
- HThread-level parallelism exists when memory accesses are clustered together to nearby memory addresses.
29Polymorphic dispatch common to object-oriented languages like Java is implemented using a
double-indirect call instruction that reads an address from memory and then jumps to it. Explain why it is
challenging to implement such an instruction without stalling in a pipelined processor.- AThe address of the next instruction to execute after the call is not known to the pipeline until the call instruction exits the memory stage and so predicting which instructions should be F, D, and E at this point is impossible without retaining execution history.
- BIf the predPC is overwritten with the address of a call at a stage earlier than memory, the instructions already in the pipeline will bubble.
- CCouldn't we all just down a bottle of bleach instead of do this midterm?
30Consider the following instruction-execution frequencies for a program running on the
standard Y86 Pipe processor. The table shows, for example, that 7% of all instructions executed read the value of a register immediately after the preceding instruction modified that register by writing into it a value that came from memory.
7% read register immediately after an instruction writes into that register a value it reads from memory
6% read register immediately after an instruction writes into that register a value computed in Execute
12% conditional jump that is taken
8% conditional jump that is not taken
5% call
5% ret
57% the remaining introduce no bubbles
What is the average cycles per instruction for this execution?- ACPI = 1 + 0.07 + 0.08 * 2 + 0.05 * 3 = 1.38
Because load-use causes 1 bubble, not taken penalties cause 2 bubbles, and ret instructions cause 3 bubbles - BCPI = 1 + 0.07 * 2 + 0.08 * 3 + 0.05 = 1.43
Because load-use causes 2 bubbles, not taken penalties cause 3 bubbles, and ret instructions cause 1 bubble - CCPI = 1 + 0.06 * 2 + 0.12 * 3 + 0.05 = 1.41
Because forwarding causes 2 bubbles, taken penalties cause 3 bubbles, and call instructions cause 1 bubble - DCPI = 1 + 0.06 + 0.12 * 2 + 0.05 * 3 = 1.45
Because forwarding causes 1 bubble, taken penalties cause 2 bubbles, and call instructions cause 3 bubbles
- ACPI = 1 + 0.07 + 0.08 * 2 + 0.05 * 3 = 1.38
31Consider the following instruction-execution frequencies for a program running on the
standard Y86 Pipe processor. The table shows, for example, that 7% of all instructions executed read the value of a register immediately after the preceding instruction modified that register by writing into it a value that came from memory.
7% read register immediately after an instruction writes into that register a value it reads from memory
6% read register immediately after an instruction writes into that register a value computed in Execute
12% conditional jump that is taken
8% conditional jump that is not taken
5% call
5% ret
57% the remaining introduce no bubbles
What is the throughput of this execution on a 3-Ghz processor (ie 3*10^9 cycles per second)? (You may go back one question to see what you chose for the answer.- A(3*10^9 / 1.38) instructions per second
- B(3*10^9 / 1.41) instructions per seconds
- C(3*10^9 / 1.43) instructions per seconds
- D(3*10^9 / 1.45) instructions per seconds
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- For when life gives you all the lemons
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- Zim Brightwood
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