Quiz
PCA_Final [arc2-1, Part-2]
Questions in this quiz (34)
1What is a Latency:
- Ais time for a single access – Main memory latency is usually >> than processor cycle time
- Bis the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
- Cis amount of data that can be in flight at the same time (Little’s Law)
2What occurs at Intruction fetches when we speak about Common And Predictable Memory Reference Patterns?
- An loop iterations
- Bsubroutine call
- Cvector access
3What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns?
- Asubroutine call
- Bn loop iterations
- Cvector access
4What occurs at Data access when we speak about Common And Predictable Memory Reference Patterns?
- Asubroutine call
- Bn loop iterations
- Cvector access
5Cache HIT:
- ANo Write Allocate, Write Allocate
- BWrite Through, Write Back
6Cache MISS:
- ANo Write Allocate, Write Allocate
- BWrite Through, Write Back
7Average Memory Access Time is equal:
- AHit Time * ( Miss Rate + Miss Penalty )
- BHit Time - ( Miss Rate + Miss Penalty )
- CHit Time / ( Miss Rate - Miss Penalty )
- DHit Time + ( Miss Rate * Miss Penalty )
8The formula of “Iron Law” of Processor Performance:
- Atime/program = instruction/program * cycles/instruction * time/cycle
- Btime/program = instruction/program * cycles/instruction + time/cycle
- Ctime/program = instruction/program + cycles/instruction * time/cycle
9Structural Hazard:
- AAn instruction in the pipeline needs a resource being used by another instruction in the pipeline
- BAn instruction depends on a data value produced by an earlier instruction
- CWhether or not an instruction should be executed depends on a control decision made by an earlier instruction
10Data Hazard:
- AAn instruction depends on a data value produced by an earlier instruction
- BAn instruction in the pipeline needs a resource being used by another instruction in the pipeline
- CWhether or not an instruction should be executed depends on a control decision made by an earlier instruction
11Control Hazard:
- AWhether or not an instruction should be executed depends on a control decision made by an earlier instruction
- BAn instruction depends on a data value produced by an earlier instruction
- CAn instruction in the pipeline needs a resource being used by another instruction in the pipeline
12What is a Bandwidth:
- Aa is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
- Bis time for a single access – Main memory latency is usually >> than processor cycle time
- Cis amount of data that can be in flight at the same time (Little’s Law)
13What is a Bandwidth-Delay Product:
- Ais amount of data that can be in flight at the same time (Little’s Law)
- Bis time for a single access – Main memory latency is usually >> than processor cycle time
- Cis the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
14What is Computer Architecture?
- Ais the design of the abstraction/implementation layers that allow us to execute information processing applications efficiently using manufacturing technologies
- Bis a group of computer systems and other computing hardware devices that are linked together through communication channels to facilitate communication and resource-sharing among a wide range of users
- Cthe programs used to direct the operation of a computer, as well as documentation giving instructions on how to use them
15Least Recently Used (LRU):
- Acache state must be updated on every access
- BUsed in highly associative caches
- CFIFO with exception for most recently used block(s)
16Cache Hit -
- AWrite Through – write both cache and memory, generally higher traffic but simpler to design
- BWrite cache only, memory is written when evicted, dirty bit per block avoids unnecessary write backs, more complicated
- CNo Write Allocate – only write to main memory
17Reduce Miss Rate: Large Cache Size.
Empirical Rule of Thumb:- AIf cache size is doubled, miss rate usually drops by about √2
- BDirect-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
- CNone of them
18Reduce Miss Rate: High Associativity.
Empirical Rule of Thumb:- ADirect-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
- BIf cache size is doubled, miss rate usually drops by about √2
- CNone of them
19What is the access time?
- ATime between when a read is requested and when the desired word arrives
- BThe minimum time between requests to memory.
- CDescribes the technology inside the memory chips and those innovative, internal organizations
- DNone of them
20What is the cycle time?
- AThe minimum time between requests to memory.
- BTime between when a read is requested and when the desired word arrives
- CThe maximum time between requests to memory.
- DNone of them
21What does SRAM stands for?
- AStatic Random Access memory
- BSystem Random Access memory
- CShort Random Access memory
- DNone of them
22What does DRAM stands for?
- ADynamic Random Access memory
- BDual Random Access memory
- CDataram Random Access memory
23Which one is concerning to fallacy?
- APredicting cache performance of one program from another
- BSimulating enough instructions to get accurate performance measures of the memory hierarchy
- CImplementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
- DOver emphasizing memory bandwidth in DRAMs
24Which one is NOT concerning to pitfall?
- APredicting cache performance of one program from another
- BSimulating enough instructions to get accurate performance measures of the memory hierarchy
- CImplementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
- DOver emphasizing memory bandwidth in DRAMs
25If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time” - ?
- AThe time between when the user enters the command and the complete response is displayed
- BThe time for the user to enter the command
- CThe time from the reception of the response until the user begins to enter the next command
26If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time” - ?
- AThe time from the reception of the response until the user begins to enter the next command
- BThe time for the user to enter the command
- CThe time between when the user enters the command and the complete response is displayed
27Little’s Law and a series of definitions lead to several useful equations for “Time server” -
- AAverage time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
- BAverage time per task in the queue
- CAverage time/task in the system, or the response time, which is the sum of Time queue and Time server
28Little’s Law and a series of definitions lead to several useful equations for “Time queue” -
- AAverage time per task in the queue
- BAverage time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
- CAverage time/task in the system, or the response time, which is the sum of Time queue and Time server
29 Little’s Law and a series of definitions lead to several useful equations for “Time system” -
- AAverage time/task in the system, or the response time, which is the sum of Time queue and Time server
- BAverage time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
- CAverage time per task in the queue
30Little’s Law and a series of definitions lead to several useful equations for “Length server” -
- AAverage number of tasks in service
- BAverage length of queue
31Little’s Law and a series of definitions lead to several useful equations for “Length queue” -
- AAverage length of queue
- BAverage number of tasks in service
32Select two-dimensional interconnection network
- AMesh
- BLinear Array
- CCross Bar
33Select multi-dimensional interconnection network
- ALinear Array
- BCross Bar
- CCube
34Select multi-dimensional interconnection network
- ALinear Array
- BCross Bar
- CHyper Cube
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- Arxitektura - gavno
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- Good Guy Beket
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- English
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